IEEE Journals & Magazines 1989 Papers Published by Researchers in Japan in 1989

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Highly contributed researchers in 1989

Kiyoo Itoh (5)

Tsutomu Yoshihara (4)

IEEE Communications Magazine

Breakup of ATT and liberalization of the telecommunications business

Author: Hideo Yoshizaki

Performance aspects of reference clock distribution for evolving digital networks

Author: Masami Kihara

Error performance in evolving digital networks including ISDNs

Authors: Yutaka Yamamoto and Tim Wright

Grade of service in the ISDN era

Authors: Tadahiro Yokoi and Kunio Kodaira

Personal telephone services using IC-cards

Authors: Naoki Matsuo, Katsunori Shimohara, Hiroyuki Matsui, Yukio Tokunaga

This list is based on the data extracted from dblp: IEEE Communications Magazine

IEEE J. Sel. Areas Communications

Soft decision decoding of block codes using received signal envelope in digital mobile radio

Author: Tadashi Matsumoto

Fast carrier-tracking coherent detection with dual-mode carrier recovery circuit for digital land mobile radio transmission

Authors: Shigeki Saito and Hiroshi Suzuki

Personal computer image communications using facsimile

Authors: Katsuhiko Hayashi and Chiaki Motegi

Identity-based information security management system for personal computer networks

Authors: Eiji Okamoto and Kazue Tanaka

Control architecture for next-generation communication networks based on distributed databases

Authors: Koso Murakami and Masafumi Katoh

An analysis of the effect of multiversions on the performance of timestamp algorithms

Authors: Jing-Fei Ren, Yutaka Takahashi, Toshiharu Hasegawa

An analog speech scrambling system using the FFT technique with high-level security

Authors: Akira Matsunaga, Keiichiro Koga, Michihisa Ohkawa

Proposal on a secure communications service element (SCSE) in the OSI application layer

Authors: Koji Nakao and Kenji Suzuki

Key distribution system based on identification information

Authors: Eiji Okamoto and Kazue Tanaka

An ID-based cryptosystem based on the discrete logarithm problem

Authors: Shigeo Tsujii and Toshiya Itoh

Variable bit-rate coding of video signals for ATM networks

Authors: Fumio Kishino, Katsutoshi Manabe, Yasuhito Hayashi, Hiroshi Yasuda

Basic characteristics of variable rate video coding in ATM environment

Authors: Mitsuru Nomura, Tetsuro Fujii, Naohisa Ohta

Packet communication protocol for image services on a high-speed multimedia LAN

Authors: Hiroshi Shimizu, Mitsuru Mera, Hideaki Tani

Missing packet recovery techniques for low-bit-rate coded speech

Authors: Junji Suzuki and Masahiro Taka

Robust design and planning of a worldwide intelligent network

Authors: Gerald R. Ash, Prosper Chemouil, Arik N. Kashper, Steven S. Katz, Katsuyuki Yamazaki, Yu Watanabe

This list is based on the data extracted from dblp: IEEE J. Sel. Areas Communications

IEEE J. Solid State Circuits

A built-in Hamming code ECC circuit for DRAMs

Authors: Kiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko

Twisted bit-line architectures for multi-megabit DRAMs

Authors: Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara

Analysis of coupling noise between adjacent bit lines in megabit DRAMs

Authors: Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode

Authors: Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

Authors: Toshihiko Shimizu, Masao Hotta, Kenji Maio, Seiichi Ueda

An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application

Authors: Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

A dual 4-bit 2-Gs/s full Nyquist analog-to-digital converter using a 70-ps silicon bipolar technology with borosenic-poly process and coupling-base implant

Authors: Valdis E. Garuts, Yeou-Chong Simon Yu, Einar O. Traa, Tadanori Yamaguchi

A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques

Authors: Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara, Tetsuro Matsumoto, Yutaka Kobayashi

A 1920(H)*1035(V) pixel high-definition CCD image sensor

Authors: Eiji Oda, Kenji Nagano, Takanori Tanaka, Nobuhiko Mutoh, Kozo Orihara

A 40-Mpixel/s bit block transfer graphics processor

Authors: Masahiko Sumi, Shigeru Tanaka, Naoyuki Kai, Yuichi Miyazawa, Masato Nagamatsu, Tsutomu Minagawa, Ichiro Nagashima, Tsuneo Hamai, Junji Mori, Tatsuo Noguchi

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance

Authors: Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara, Tetsuro Matsumoto

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode

Authors: Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

A fast-settling op amp with low supply current

Authors: Robert J. Widlar and Mineo Yamatake

New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier

Authors: Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh

High-density quaternary logic array chip for knowledge information processing systems

Authors: Takahiro Hanyu and Tatsuo Higuchi

A 5.6 MIPS call-handling processor for switching systems

Authors: Takao Hayashi, Yasuaki Saita, Toshiaki Ohno, Takashi Morita, Takuma Fukuda, Shinji Yoshida, Renya Ikeda

A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

Authors: Masao Ida, Naoki Kato, Tohru Takada

Gigahertz-band high-gain GaAs monolithic amplifiers using parallel feedback technique

Authors: Noboru Ishihara, Hiroyuki Kikuchi, Mamoru Ohara

A 300 MHz monolithic video current driver for high-resolution CRT applications

Authors: Kazuo Kato, Hideo Sato, Yasuji Kamata, Kenkichi Yamashita, Seiichi Ueda

1.5 mu m CMOS gate arrays with analog/digital macros designed using common base arrays

Authors: Shigeru Kawada, Yasunori Hara, Toshio Isono, Teruo Inuzuka

A 1 kbit Josephson random access memory using variable threshold cells

Authors: Itaru Kurosawa, Hiroshi Nakagawa, Shin Kosaka, Masahiro Aoyagi, Susumu Takada

A 17 bit oversampling D-A conversion technology using multistage noise shaping

Authors: Yasuyuki Matsuya, Kuniharu Uchimura, Atsushi Iwata, Takao Kaneko

Improvement of soft-error rate in MOS SRAMs

Authors: Shuji Murakami, Katsuki Ichinose, Kenji Anami, Shimpei Kayano

A Josephson 4 bit RALU for a prototype computer

Authors: Hiroshi Nakagawa, Shin Kosaka, Hiroki Kawamura, Itaru Kurosawa, Masahiro Aoyagi, Youichi Hamazaki, Yoshikuni Okada, Susumu Takada

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Authors: Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

New nibbled-page architecture for high-density DRAMs

Authors: Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi

A 20 kbit associative memory LSI for artificial intelligence machines

Authors: Takeshi Ogura, Junzo Yamada, Shin-Ichiro Yamada, Masa'aki Tan'no

A 32 kbyte integrated cache memory

Authors: Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato

An experimental BiCMOS video 10 bit ADC

Authors: Yasuhiro Sugimoto and Satoshi Mizoguchi

An 8 ns 256 K BiCMOS RAM

Authors: Nobuo Tamba, Shuuichi Miyaoka, Masanori Odaka, Katsumi Ogiue, Kouichirou Yamada, Takahide Ikeda, Mitsuru Hirao, Hisayuki Higuchi, Hideaki Uchida

Design of a 32 bit microprocessor, TX1

Authors: Takeji Tokumaru, Eeji Masuda, Chikahiro Hori, Kimiyoshi Usami, Misao Miyata, Jun Iwamura

A new CR-delay circuit technology for high-density and high-speed DRAMs

Authors: Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

VLSI implementation of a variable-length pipeline scheme for data-driven processors

Authors: Tetsuo Yamasaki, Kenji Shima, Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Hiroaki Terada

A 1.5-V DRAM for battery-based applications

Authors: Masakazu Aoki, Jun Etoh, Kiyoo Itoh, Shin Kimura, Yoshifumi Kawamoto

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register

Authors: Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano

A 60-ns 16-Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance

Authors: Shizuo Chou, Tsuneo Takano, Akio Kita, Fumio Ichikawa, Masaru Uesugi

A 45-ns 16-Mbit DRAM with triple-well structure

Authors: Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Sejii Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto, Koichi Toita

A 4-bit Josephson data processor chip

Authors: Yuji Hatano, Shinichiro Yano, Hiroyuki Mori, Hiroji Yamada, Mikio Hirano, Ushio Kawabe

30-ps 7.5-GHz GaAs MESFET macrocell array

Authors: Masayuki Ino, Minoru Togashi, Shoji Horiguchi, Masahiro Hirayama, Hideki Kataoka

Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic

Authors: Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit

Authors: Katsuyuki Kaneko, Tadashi Okamoto, Masaitsu Nakajima, Yasuhiro Nakakura, Satoshi Gokita, Junji Nishikawa, Yuji Tanikawa, Hiroshi Kadota

Substrate current reduction techniques for BiCMOS DRAM

Authors: Takayuki Kawahara, Goro Kitsukawa, Hisayuki Higuchi, Yoshiki Kawajiri, Takao Watanabe, Kiyoo Itoh, Ryoichi Hori, Yutaka Kobayashi, Tetsuro Matsumoto

A 54000-gate ECL array with substrate power supply

Authors: Masayuki Kokado, Makoto Yoshida, Norihito Miyoshi, Kouichi Suzuki, Matsuo Takaoka, Norihisa Tsuzuki, Hideki Harada

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme

Authors: Shinji Komori, Hidehiro Takata, Todhixuki Tamura, Fumixsdu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Hiroaki Nishikawa, Hiroaki Terada

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Authors: Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano

Estimation of the energy of cytoplasmic movements by magnetometry: effects of temperature and intracellular concentration of ATP

Authors: Iku Nemoto, Kazuhito Ogura, Hideki Toyotama

Functional neuromuscular stimulation system using an implantable hydroxyapatite connector and a microprocessor-based portable stimulator

Authors: Kenzo Akazawa, Masaaki Makikawa, Jiro Kawamura, Hideki Aoki

Development of percutaneous intramuscular electrode for multichannel FES system

Authors: Yasunobu Handa, Nozomu Hoshimiya, Yasutaka Iguchi, Takashi Oda

A multichannel FES system for the restoration of motor functions in high spinal cord injury patients: a respiration-controlled system for multijoint upper extremity

Authors: Nozomu Hoshimiya, Akira Naito, Michihiro Yajima, Yasunobu Handa

Orderly stimulation of skeletal muscle motor units with tripolar nerve cuff electrode

Authors: Richard V. Baratta, Masayoshi Ichie, Sung Kwan Hwang, Moshe Solomonow

A method for recovering physiological components from dynamic radionuclide images using the maximum entropy principle: a numerical investigation

Authors: Masahiko Nakamura, Yutaka Suzuki, Shin Kobayashi

A parametric modeling of membrane current fluctuations with its application to the estimation of the kinetic properties of single ionic channels

Authors: Hiroyuki Mino and Kazuo Yana

Discrimination of synthetic vowels by using tactile vocoder and a comparison to that of an eight-channel cochlear implant

Author: Tohru Ifukube

This list is based on the data extracted from dblp: IEEE Transactions Biomedical Eng.