This webpage may contain errors. Please do NOT trust the following list, although the maintainer has tried his best to correct the mistakes. If you find an error, please contact the maintainer via email at “contact [at] ishikawa.cc”.

Highly contributed researchers in 1996

Koichiro Mashiko (6)

Hiroaki Suzuki (4) / Tadashi Sumi (4)

Enterprise Networking [Guest Editorial]

Authors: David Kirsch, Branislav Meandzija, Karen Seo, Douglas N. Zuckerman

The TPC-5 Cable Network

Authors: W. Christopher Barnett, Hitoshi Takahira, James C. Baroni, Yoshihiro Ogi

The Asia Pacific Cable Network

Authors: David R. Gunderson, Antoine Lecroart, Koichi Tatekura

The FLAG cable system

Authors: Thomas Welsh, Roger Smith, Haruo Azami, Raymond Chrisner

The TINA network resource model

Authors: Magnus Lengdell, Juan Pavn, Masaki Wakano, Martin Chapman, Motoharu Kawanishi

Perspective for super-high-definition image systems

Authors: Sadayasu Ono and Junji Suzuki

Communications in the Medical Environment [Guest Editorial]

Authors: Christos Douligeris, Matthias Kaiserswerth, Hiroshi Takeda

Development and operation of PACS/teleradiology in Japan

Authors: Kiyonari Inamura, Hiroshi Kondoh, Hiroshi Takeda

Social Aspects of Emerging Information Infrastructures [Guest Editorial]

Authors: Raymond L. Pickholtz, Stephen B. Weinstein, Tetsuya Miki

ATM transport network operation system in Japan

Authors: Nobuo Fujii and Tetsuya Yamamura

Wideband CDMA system for personal radio communications

Authors: Atsushi Fukasawa, Takuro Sato, Yumi Takizawa, Toshio Kato, Manabu Kawabe, Reed E. Fisher

Road vehicle communication system for vehicle control using leaky coaxial cable

Authors: Makoto Nakamura, Hiroshi Tsunomachi, Ryotaro Fukui

Guest editorial: Communications for the intelligent transportation system

Authors: Yorgos J. Stephanedes, Christos Douligeris, Sadao Takaba

Cable access beyond the hype: on residential broadband data services over HFC networks

Authors: Chatschik Bisdikian, Kiyoshi Maruyama, David I. Seidman, Dimitrios N. Serpanos

Performance issues in public ABR service

Authors: Hiroshi Saito, Konosuke Kawashima, Hideo Kitazume, Arata Koike, Mika Ishizuka, Atsushi Abe

A new service provisioning method in the multimedia/B-ISDN era

Authors: Hisazumi Tsuchida and Kisaku Fujimoto

This list is based on the data extracted from dblp: IEEE Communications Magazine

Using Timed CSP for Specification Verification and Simulation of Multimedia Synchronization

Authors: Ahmet Feyzi Ates, Murat Bilgic, Senro Saito, Behet Sarikaya

A High Prformance Switch for OC-12 SONET Self-Healing Ring Networks

Authors: Masahiro Takatori, Yukio Nakano, Yoshihiro Ashi, Hiroyuki Fujita, Masao Mizukami, Kunihiro Itoh

Throughput analysis of DS/SSMA unslotted ALOHA system with fixed packet length

Authors: Takahide Sato, Hiraku Okada, Takaya Yamazato, Masaaki Katayama, Akira Ogawa

OAM Framework for Multiwavelength Photonic Transport Network (Invited Paper)

Authors: Yasuhiko Tada, Yukio Kobayashi, Yoshiaki Yamabayashi, Shinji Matsuoka, Kazuo Hagimoto

A Super Wideband Optical FM Modulation Scheme for Video Transmission Systems

Authors: Koji Kikushima, Hisao Yoshinaga, Hiroshi Nakamoto, Chisei Kishimoto, Masami Kawabe, Ko-Ichi Suto, Kiyomi Kumozaki, Nori Shibata

Quality-Based Evaluation of Multimedia Synchronization Protocols for Distributed Multimedia Information Systems

Authors: Shahab Baqai, M. Farrukh Khan, Miae Woo, Seiichi Shinkai, Ashfaq A. Khokhar, Arif Ghafoor

Transmit Permission Control on Spread ALOHA Packets in LEO Satellite Systems

Authors: Abbas Jamalipour, Masaaki Katayama, Takaya Yamazato, Akira Ogawa

Performance of Chip Coding in FFH SSMA Systems

Authors: Hiroyuki Yashima, Qiang Wang, Vijay K. Bhargava

This list is based on the data extracted from dblp: IEEE J. Sel. Areas Communications

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

Authors: Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki

A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment

Authors: Shoji Otaka, Takafumi Yamaji, Ryuichi Fujimoto, Chikau Takahashi, Hiroshi Tanimoto

A fully compensated active pull-down ECL circuit with self-adjusting driving capability

Authors: Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko

An adjustment-free single-chip video signal processing LSI for VHS VCR's

Authors: Norihisa Yamamoto, Osamu Nakagawa, Kenji Takebuchi, Yukinori Kitamura

A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

Authors: Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima, Masaoki Ishikawa, Muneo Fukaishi, Hikam Hida, Yasuo Ohno

A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator

Authors: Tsuneo Tsukahara, Masayuki Ishikawa, Masahiro Muraguchi

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond

Authors: Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami

A 90-MHz 16-Mb system integrated memory with direct interface to CPU

Authors: Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs

Authors: Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki

A current direction sense technique for multiport SRAM's

Authors: Masanori Izumikawa and Masakazu Yamashina

An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

Authors: Hideyuki Kabuo, Minoru Okamoto, Isao Tanaka, Hiroyuki Yasoshima, Shinichi Marui, Masayuki Yamasaki, Toshio Sugimura, Katsuhiko Ueda, Toshihlro Ishikawa, Hidetoshi Suzuki, Ryuichi Asahi

Fault-tolerant designs for 256 Mb DRAM

Authors: Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

Authors: Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto

A 286 MHz 64-b floating point multiplier with enhanced CG operation

Authors: Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

Authors: Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture

Authors: Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ

Authors: Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii

Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits

Authors: Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta

A GaAs MMIC chip-set for mobile communications using on-chip ferroelectric capacitors

Authors: Haruhiko Koizumi, Atsushi Noma, Tsuyoshi Tanaka, Kunihiko Kanazawa, Daisuke Ueda

A 1.2 GFLOPS neural network chip for high-speed neural network servers

Authors: Yoshikazu Kondo, Yuichi Koshiba, Yutaka Arima, Mitsuhiro Murasaki, Tuyoshi Yamada, Hiroyuki Amishiro, Hakuro Mori, Kazuo Kyuma

Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability

Authors: Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

Authors: Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko

A GHz MOS adaptive pipeline technique using MOS current-mode logic

Authors: Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

Authors: Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko

Top-down pass-transistor logic design

Authors: Kazuo Yano, Yasuhiko Sasaki, Kunihito Rikino, Koichi Seki

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Authors: Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto

A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

Authors: Hiroalti Murakami, Naoka Yano, Yukio Ootaguro, Yukio Sugeno, Maki Ueno, Yukinori Muroya, Tsuneo Aramaki

A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication

Authors: Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi

Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor

Authors: Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta

Over-30-GHz limiting amplifier ICs with small phase deviation for optical communication systems

Authors: Makoto Nakamura, Yuhki Imai, Shoji Yamahata, Yohtaro Umeda

Leading-zero anticipatory logic for high-speed floating point addition

Authors: Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

Authors: Tadashi Maeda, Keiichi Numata, Masahiro Fujii, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa

A 29-ns 64-Mb DRAM with hierarchical array architecture

Authors: Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

Authors: Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta

A low-power 128×1-bit GaAs FIFO for ATM packet switcher

Authors: Hidetoshi Kawasaki and Stephen I. Long

High power DPDT antenna switch MMIC for digital cellular systems

Authors: Kazumasa Kohama, Takahiro Ohgihara, Yoshikazu Murakami

A 2.4 Gb/s receiver and a 1: 16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor

Authors: Fumihiko Sato, Hiroshi Tezuka, Masaaki Soda, Takasuke Hashimoto, Tetsuyuki Suzaki, Tom Tatsumi, Takenori Morikawa, Tsutomu Tashiro

A parallel processing chip with embedded DRAM macros

Authors: Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter

Design of a one-transistor-cell multiple-valued CAM

Authors: Takahiro Hanyu, N. Kanagawa, Michitaka Kameyama

Design of a one-transistor-cell multiple-valued CAM

Authors: Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama

Low-power video encoder/decoder chip set for digital VCRs

Authors: Katsuya Hasegawa, Kazutake Ohara, Akihisa Oka, Takehiro Kamada, Yasuhiro Nagaoka, Katsuhisa Yano, Eiji Yamauchi, Takao Kashiro, Tomoo Nakagawa

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories

Authors: Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

Authors: Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihira Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Authors: Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

Authors: Tohru Miwa, Hachiro Yamada, Yoshinori Hirota, Toshiya Satoh, Hideki Hara

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators

Authors: Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application

Authors: Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada

A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell

Authors: Masayoshi Ohkawa, Hiroshi Sugawara, Naoaki Sudo, Masaru Tsukiji, Ken-ichiro Nakagawa, Masato Kawata, Ken-ichi Oyama, Toshio Takeshima, Shuichi Ohya

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

Authors: Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John Mark Drynan, Masahiro Komuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko ichinose, Tomoo imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, Takashi Okuda

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

Authors: Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding

Authors: Kazuhito Suguri, Toshihiro Minami, Hiroaki Matsuda, Ritsu Kusaba, Toshio Kondo, Ryota Kasai, Takumi Watanabe, Hidenuri Sato, Nobutarou Shibata, Yutaka Tashiro, Takaaki Izuoka, Atsushi Shimizu, Hiroshi Kotera

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM

Authors: Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI

Authors: Sanroku Tsukamoto, I. Dedic, Toshiaki Endo, K. y. Kikuta, K. Goto, O. Kobayashi

200-MHz superscalar RISC microprocessor

Authors: Nader Vasseghi, Kenneth Yeager, Egino Saito, Mahdi Seddighnezhad

A 3-V, 2%-mW multibit current-mode ΣΔ DAC with 100 dB dynamic range

Authors: Toshihiko Hamasaki, Yoshiaki Shinohara, Hitoshi Terasawa, Kou-Ichirou Ochiai, Masaya Hiraoka, Hideki Kanayama

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology

Authors: Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida

A 1.9-GHz single chip IF transceiver for digital cordless phones

Authors: Hisayasu Sato, Kenichi Kashiwagi, Kazuhito Niwano, Tetsuya Iga, Tatsuhiko Ikeda, Koichiro Mashiko, Tadashi Sumi, Koji Tsuchihashi

An offset-free LPF for π/4-shift QPSK signal generator

Authors: Hiroshi Tanimoto, Tetsuro Itakura, Takashi Ueno, Akira Yasuda, Kazuhiro Oda

A single-chip GaAs RF transceiver for 1.9-GHz digital mobile communication systems

Authors: Kazuya Yamamoto, Kosei Maemura, Nobuyuki Kasai, Yutaka Yoshii, Yukio Miyazaki, Masatoshi Nakayama, Noriko Ogata, Tadashi Takagi, Mutsuyuki Otsubo

This list is based on the data extracted from dblp: IEEE J. Solid State Circuits

Network management research in ATDNet

Authors: Robert D. Doverspike, Mari Maeda, Sanjai Narain, Jorge L. Pastor, Chien-Chung Shen, Ned G. Stoffel, Yukun Tsai, Brian J. Wilson

This list is based on the data extracted from dblp: IEEE Networking

Analysis of LPC/DFT features for an HMM-based alphadigit recognizer

Authors: Daniel J. Mashao, Yoshihiko Gotoh, Harvey F. Silverman

Blind phase recovery in QAM communication systems using higher order statistics

Authors: Ling Chena, Hiroji Kusaka, Masanobu Kominami

This list is based on the data extracted from dblp: IEEE Signal Processing Letters

Guest Editors' Foreword

Authors: Hamid Gharavi, Hiroshi Yasuda, Teresa H. Meng

This list is based on the data extracted from dblp: IEEE Transactions Circuits Systems Video Technol.

Aliasing Error for a Mask ROM Built-In Self-Test

Authors: Kazuhiko Iwasaki and Shigeo Nakamura

Probability to Achieve TSC Goal

Authors: Jien-Chung Lo and Eiji Fujiwara

Author's Reply

Authors: Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers

Authors: Yooichi Shintani, Toru Shonai, Hiroshi Kurokawa, Kazunori Kuriyama, Akira Yamaoka

Fast Gossiping on Mesh-Bus Computers

Authors: Satoshi Fujita and Masafumi Yamashita

This list is based on the data extracted from dblp: IEEE Transactions Computers

A fuzzy-Gaussian neural network and its application to mobile robot control

Authors: Keigo Watanabe, Jun Tang, Masatoshi Nakamura, Shinji Koga, Toshio Fukuda

Application of gain scheduled H∞ robust controllers to a magnetic bearing

Authors: Fumio Matsumura, Toru Namerikawa, Kazuhiro Hagiwara, Masayuki Fujita

Stability analysis of self-sensing magnetic bearing controllers

Authors: Takeshi Mizuno, Kenji Araki, Hannes Bleuler

μ synthesis of flexible rotor-magnetic bearing systems

Authors: Kenzo Nonami and Takayuki Ito

Levitation and torque control of internal permanent magnet type bearingless motor

Authors: Yohji Okada, Shigenobu Miyamoto, Tetsuo Ohishi

This list is based on the data extracted from dblp: IEEE Transactions Control. Systems Technol.

A new efficient approach for the removal of impulse noise from highly corrupted images

Authors: Eduardo Abreu, Michael Lightstone, Sanjit K. Mitra, Kaoru Arakawa

Adaptive transforms for image coding using spatially varying wavelet packets

Authors: Kannan Ramchandran, Zixiang Xiong, Kohtaro Asai, Martin Vetterli

This list is based on the data extracted from dblp: IEEE Transactions Image Processing

Dextrous hand grasping force optimization

Authors: Martin Buss, Hideki Hashimoto, John B. Moore

Hybrid position/force control of flexible-macro/rigid-micro manipulator systems

Authors: Tsuneo Yoshikawa, Kensuke Harada, Atsushi Matsumoto

Visual servoing with hand-eye manipulator-optimal control approach

Authors: Koichi Hashimoto, Takumi Ebine, Hidenori Kimura

Estimating precise edge position by camera motion

Authors: Koji Kato, Hiroshi Ishiguro, Saburo Tsuji

Subspace methods for robot vision

Authors: Shree K. Nayar, Sameer A. Nene, Hiroshi Murase

This list is based on the data extracted from dblp: IEEE Transactions Robotics Autom.

Subadaptive piecewise linear quantization for speech signal (64 kbit/s) compression

Authors: Hiroto Saito, Isao Umoto, Akira Sasou, Shogo Nakamura, Yoshihiko Horio, Tahiro Kubota

An 8-kb/s conjugate structure CELP (CS-CELP) speech coder

Authors: Akitoshi Kataoka, Takehiro Moriya, Shinji Hayashi

This list is based on the data extracted from dblp: IEEE Transactions Speech Audio Processing

Retrieving quality video across heterogeneous networks. Video over wireless

Authors: Jos M. F. Moura, Radu S. Jasinschi, Hirohisa Shiojiri, Jyh-Cherng Lin

ATM wireless access for mobile multimedia: concept and architecture

Authors: Masahiro Umehira, Masamitsu Nakura, Hijin Sato, Akira Hashimoto

This list is based on the data extracted from dblp: IEEE Wirel. Communications

Virtual path routing for survivable ATM networks

Authors: Kazutaka Murakami and Hyong S. Kim

This list is based on the data extracted from dblp: IEEE/ACM Transactions Networking

Optical information processing and beyond

Authors: Yoshiki Ichioka, Tadao Iwaki, Katsunori Matsuoka

Speckle reduction in coherent information processing

Authors: Toshiaki Iwai and Toshimitsu Asakura

Behind the scenes of virtual reality: vision and motion

Authors: Hitoshi Ohzu and Kohei Habara

Optical scanning holography

Authors: Ting-Chung Poon, Ming Hsien Wu, Kazunori Shinoda, Yoshiji Suzuki

Optical computing and interconnects

Authors: Toyohiko Yatagai, Shigeru Kawai, Hongxin Hijang

Corrections to "Optical Scanning Holography"

Authors: Ting-Chung Poon, Ming Hsien Wu, Kazunori Shinoda, Yoshiji Suzuki

This list is based on the data extracted from dblp: Proc. IEEE