IEEE Journals & Magazines 1990

Norio Takato (4) / Toshiharu Hasegawa (4)

Speech coding technology for ATM networks

Authors: Nobuhiko Kitawaki, Hiromi Nagabuchi, Masahiro Taka, Kenzo Takahashi

Echo cancellation and applications

Authors: Kazuo Murano, Shigeyuki Unagami, Fumio Amano

Speech synthesis from text

Author: Yoshinori Sagisaka

Customer control of network management from the service provider's perspective

Authors: Makoto Yoshida, Makoto Kobayashi, Haruo Yamaguchi

Technologies towards broadband ISDN

Authors: Kazuo Murano, Koso Murakami, Eisuke Iwabuchi, Toshio Katsuki, Hiroshi Ogasawara

Migration to broadband ISDN

Author: Iwao Toda

Disaster prevention measures of NTT for telecommunications network systems

Authors: Yasuo Adachi and Hiroki Obata

Current role and future evolution of the ISDN Signaling system in NTT's network

Authors: Kenichi Kitami and Kazuhiko Ogawa

Common channel signaling for international service applications

Authors: John J. Lawser, Jun Matsumoto, J. Martin Pigott

CCITT standardization of network node interface of synchronous digital hierarchy

Authors: Koichi Asatani, Keith R. Harrison, Ralph Ballart

Synchronous digital transmission systems based on CCITT SDH standard

Authors: Hiroyuki Kasai, Takehiro Murase, Hiromi Ueda

Dynamic operation and maintenance systems for switching networks

Authors: Takahiro Miyazaki, Moo Wan Kim, Masaaki Wakamoto

Advanced traffic control methods for network management

Authors: Kenichi Mase and Hisao Yamamoto

Dynamic routing schemes for international networks

Authors: Yu Watanabe and Toshikane Oda

This list is based on the data extracted from dblp: IEEE Commun. Mag.

Feasibility Study for Worldwide Videotex Interworking

Authors: Koji Nakao, Sadao Obana, Satoshi Nishiyama, Toshiaki Tanaka

Structural Way of Thinking as Applied to Quality Assurance Management

Authors: Zenya Koono and Masahiro Soga

Interactive Specification Environment for Communication Service Software

Authors: Yoshihiro Nitsu and Osamu Mizuno

High-Quality Software Development System - AYUMI

Authors: Masahiro Toyama, Mamoru Sugawara, Kiyoh Nakamura

Achieving Multimedia Communications on a Heterogeneous Network

Authors: Ching-Hua Chow and Motomitsu Adachi

Analysis of a Discrete-Time Single-Server Queue with Bursty Inputs for Traffic Control in ATM Networks

Authors: Masayuki Murata, Yuji Oie, Tatsuya Suda, Hideo Miyahara

Network Control Method and Human-Machine Interface Design for ISDN Multimedia Terminal

Authors: Shizuo Nakano, Naofumi Nagai, Ritsuo Sawada, Osamu Miyagishi

Combination of an Adaptive Array Antenna and a Canceller of Interference for Direct-Sequence Spread-Spectrum Multiple-Access System

Authors: Ryuji Kohno, Hideki Imai, Mitsutoshi Hatori, Subbarayan Pasupathy

An Adaptive Canceller of Cochannel Interference for Spread-Spectrum Multiple-Access Communication Networks in a Power Line

Authors: Ryuji Kohno, Hideki Imai, Mitsutoshi Hatori, Subbarayan Pasupathy

Optical Heterodyne Image-Rejection Receiver for High-Density Optical Frequency Division Multiplexing System

Authors: Terumi Chikama, Takao Naito, Shigeki Watanabe, Tetsuya Kiyonaga, Masuo Suyama, Hideo Kuwahara

Integrated Optical Multi-/Demultiplexer Using Acoustooptic Effect for Multiwavelength Optical Communications

Authors: Nobuo Goto and Yasumitsu Miyazaki

Distributed Feedback Laser Arrays Fabricated by Synchrotron Orbital Radiation Lithography

Authors: Masashi Nakao, Kenji Sato, Toshio Nishida, Toshiaki Tamamura

A 16-Channel Frequency Selection Switch for Optical FDM Distribution Systems

Authors: Kazuhiro Oda, Norio Takato, Toshimi Kominato, Hiromu Toba

Transmission Limitations Due to Fiber Nonlinearities in Optical FDM Systems

Authors: Nori Shibata, Kiyoshi Nosu, Katsushi Iwashita, Yuji Azuma

Frequency Separation Locking and Synchronization for FDM Optical Sources Using Widely Frequency Tunable Laser Diodes

Authors: Naoki Shimosaka, Kazuhisa Kaede, Masahiko Fujiwara, Shuntaro Yamazaki, Shigeru Murata, Makoto Nishio

Laser-Trimming Adjustment of Waveguide Birefringence in Optical FDM Components

Authors: Akio Sugita, Kaname Jinguji, Norio Takato, Masao Kawachi

Silica-Based Integrated Optic Mach-Zehnder Multi/Demultiplexer Family with Channel Spacing of 0.01-250 nm

Authors: Norio Takato, Toshimi Kominato, Akio Sugita, Kaname Jinguji, Hiromu Toba, Masao Kawachi

Factors Affecting the Design of Optical FDM Information Distribution Systems

Authors: Hiromu Toba, Kazuhiro Oda, Kiyoshi Nosu, Norio Takato

Fiber-Optic Subcarrier Multiplexing Video Transport Employing Multilevel QAM

Authors: Norio Kanno and Katsuyoshi Ito

FM-FDM Optical CATV Transmission Experiment and System Design for MUSE HDTV Signals

Authors: Mikio Maeda and Makoto Yamamoto

Optical Receiver for VHF Multichannel Video Transmission

Authors: Yasushi Takahashi, Katsuyuki Nagano, Yoshitaka Takasaki

Distributed Feedback Laser Diode and Module for CATV Systems

Authors: Akira Takemoto, Hitoshi Watanabe, Yasuo Nakajima, Yasushi Sakakibara, Syoichi Kakimoto, Junichiro Yamashita, Tatsuo Hatta, Yoshio Miyake

Erbium Doped Fiber Amplifier for Video Distribution Networks

Authors: Etsugo Yoneda, Koji Kikushima, Toshiyuki Tsuchiya, Ko-Ichi Suto

Application of Advanced Microelectronics to Large-Scale Communication Equipment - Compact and Maintenance-Free TDMA Equipment

Authors: Shuzo Kato, Masahiro Morikura, Masahiro Umehira, Kiyoshi Enomoto, Shuji Kubota

A 2 Gb/s Expandable Space-Division Switching LSI and Network Architecture for Gigabit-Rate Broad-Band Circuit Switching

Authors: Naoaki Yamanaka, Shiro Kikuchi, Masao Suzuki, Yukiharu Yoshioka

This list is based on the data extracted from dblp: IEEE J. Sel. Areas Commun.

A speed-enhanced DRAM array architecture with embedded ECC

Authors: Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima

An experimental 1-Mbit cache DRAM with ECC

Authors: Mikio Asakura, Yoshio Matsuda, Hidaka Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima

A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs

Authors: Tohru Furuyama, Hidemi Ishiuchi, Hiroyasu Tanaka, Yoshihisa Watanabe, Yusuke Kohyama, Tohru Kimura, Kazuyoshi Muraoka, Souichi Sugiura, Kenji Natori

High-performance BiCMOS 100 K-gate array

Authors: James D. Gallia, Ah-Lyan Yee, Kwok Kit Chau, I-Fay Wang, Harvey Davis, Shobana Swamy, Van M. Nguyen, Kamalesh Natvarlal Ruparel, Kermit Moore, Brian Chae, Carl E. Lemonds, Pat Eyres, Toshiaki Yoshino, Ashwin Shah

An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption

Authors: Shiro Hosotani, Takahiro Miki, Atsushi Maeda, Nobuharu Yazawa

A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design

Authors: Kenichi Imamiya, Jun-ichi Miyamoto, Shigeru Atsumi, Nobuaki Ohtsuka, Yukinori Muroya, Toshiyuki Sako, Masao Higashino, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Hitoshi Araki, Yukio Kaneko, Kazuhito Narita, Norihisa Arai, Kuniyoshi Yoshikawa, Shinichi Tanaka

An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell

Authors: Koichiro Ishibashi, Toshiaki Yamanaka, Katsuhiro Shimohigashi

A CMOS 510 K-transistor single-chip token-ring LAN controller (TRC) compatible with IEEE802.5 MAC protocol

Authors: Akira Kanuma, Toshiyuki Yaguchi, Koichi Tanaka, Eiichi Katsumata, Katsuhito Fujimoto, Yuuichi Miyazawa, Shinichi Iida, Takeshi Yamamoto

Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems

Authors: Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi

A high-speed parallel sensing architecture for multi-megabit flash E2PROMs

Authors: Kiyoteru Kobayashi, Tatsuo Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara

A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier

Authors: Hisakazu Kotani, Hironori Akamatsu, Junko Matsushima, Shozo Okada, Tsuyoshi Shiragasawa, Takayoshi Yamada, Michihiro Inoue

A subnanosecond clock Josephson 4-bit processor

Authors: Seigo Kotani, Takahiro Imamura, Shinya Hasuo

Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system

Authors: Mitsumasa Koyanagi, Hidehiro Takata, Hiroki Mori, Junichiro Iba

A multibit test trigger circuit for megabit SRAMs

Authors: Fumio Miyaji, Takashi Emori, Yasushi Matsuyama, Yoshikazu Kanaishi, Katsunori Seno, Yoshiaki Hagiwara

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC

Authors: Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka

Decoded-source sense amplifier for high-density DRAMs

Authors: Jun-ichi Okamura, Yoshio Okada, Masaru Koyanagi, Yoshiaki Takeuchi, Masahiro Yamada, Kiyofumi Sakurai, Sadao Imada, Suzuo Saito

Jitter analysis of high-speed sampling systems

Authors: Mitsuru Shinagawa, Yukio Akazawa, Tsutomu Wakimoto

A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs

Authors: Masao Suzaki, Naoki Yamanaka, Michihiro Hirata, Shiro Kikuchi

A 100-mega-access per second matching memory for a data-driven microprocessor

Authors: Hidehiro Takata, Shinji Komori, Toshiyuki Tamura, Fumiyasu Asai, Hisakazu Sato, Takio Ohno, Takeshi Tokuda, Hiroki Nishikawa, Hirofumi Terada

The stabilized reference-line (SRL) technique for scaled DRAMs

Authors: Kenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka

An on-chip smart memory for a data-flow CPU

Authors: Gregory A. Uvieghara, Yoshinobu Nakagome, Deog-Kyoon Jeong, David A. Hodges

A low-power wide-band amplifier using a new parasitic capacitance compensation technique

Authors: Tsutomu Wakimoto and Yukio Akazawa

A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers

Authors: Hiroyuki Yamauchi, Toshiki Yabu, Takayoshi Yamada, Michihiro Inoue

A no-trimming SLIC two-chip set with coin telephone signaling facilities

Authors: Masao Akata, Yuichiro Nagataki, Kunihiro Koyabu, Kanji Mukai, Shinji Yoshida, Shegehi Morisaki, Masahiro Eda, Isamu Ueki, Toru Matsui

An integrated switched-capacitor signal processing design system

Authors: Allen R. Barlow, Kaoru Takasuka, Yasunori Nambu, Toshio Adachi, Jun-Ichi Konno, Mineo Nishimoto, Shiro Suzuki, Kenji Nemoto, Kohji Takashima

A built-in self-test algorithm for row/column pattern sensitive faults in RAMs

Authors: Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita

The SDC cell-A novel design methodology for high-speed arithmetic modules using CMOS/BiCMOS precharged circuits

Authors: Takehisa Hayashi, Toshio Doi, Mitsuo Asai, Kenichi Ishibashi, Shoji Shukuri, Atsuo Watanabe, Makoto Suzuki

A high-density NAND EEPROM with block-page programming for microcomputer applications

Authors: Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Ryouhei Kirisawa, Seiichi Aritome, Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka

Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM

Authors: Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Tetsuya Aono, Ikuo Ogoh, Michihiro Yamada

A 15-ns 32*32-b CMOS multiplier with an improved parallel structure

Authors: Masato Nagamatsu, Shigeru Tanaka, Junji Mori, Katsusi Hirano, Tatsuo Noguchi, Kazuhisa Hatanaka

Operational-amplifier compilation with performance optimization

Authors: Hidetoshi Onodera, Hiroyuki Kanbara, Keikichi Tamaru

Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas

Authors: Takayasu Sakurai and A. Richard Newton

An ECL-compatible GaAs SCFL design method

Authors: Shoichi Shimizu, Kunio Yoshihara, Toshiyuki Terada, Kenji Ishida, Yoshiaki Kitaura, Chiaki Takubo

A BiCMOS technology with 660-MHz vertical p-n-p transistor for analog/digital ASICs

Authors: Katsumoto Soejima, Akira Shida, Hiroshi Koga, Junnichi Ukai, Hiroshi Sata, Masaki Hirata

A VLSI fuzzy logic controller with reconfigurable, cascadable architecture

Authors: Hiroyuki Watanabe, Wayne D. Dettloff, Kathy E. Yount

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic

Authors: Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu

A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library

Authors: Takashi Hotta, Tadaaki Bandoh, Atsuo Hotta, Tetsuo Nakano, Shoji Iwamoto, Shigemi Adachi

Trends in megabit DRAM circuit design

Author: Kiyoo Itoh

A single-power-supply 10-b video BiCMOS sample-and-hold IC

Authors: Kazunori Tsugaru, Yasuhiuro Sugimoto, Makoto Noda, Takao Ito, Yoshito Suwa

A Josephson 10-b instruction 128-word ROM unit

Authors: Masahiro Aoyagi, Hiroshi Nakagawa, Itaru Kurosawa, Shin Kosaka, Yoshikuni Okada, Youichi Hamazaki, Susumu Takada

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM

Authors: Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama

Design and application of a GaAs digital RF memory chip

Authors: William A. White, Albert H. Taddiken, Hisashi Shichijo, Michael A. Vernon, David A. Whitmire

A 15-ns 4-Mb CMOS SRAM

Authors: Shingo Aizaki, Toshiyuki Shimizu, Masayoshi Ohkawa, Kazuhiko Abe, Akane Aizaki, Manabu Ando, Osamu Kudoh, Isao Sasaki

A static RAM chip with on-chip error correction

Authors: Tzi-Dar Chiueh, Rodney M. Goodman, Masahiro Sayano

A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture

Authors: Toshihiko Hirose, Hirotada Kuriyama, Shuji Murakami, Kojiro Yuzuriha, Takao Mukai, Kazuhito Tsutsumi, Yasumasa Nishimura, Yoshio Kohno, Kenji Anami

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

Authors: Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto

A 23-ns 1-Mb BiCMOS DRAM

Authors: Goro Kitsukawa, Kazumasa Yanagisawa, Yutaka Kobayashi, Yoshitaka Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Hitoshi Miwa, Hiroyuki Miyazawa, Yoshiki Kawajiri, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto, Kiyoo Itoh

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Authors: Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

A 16-ns 1-Mb CMOS EPROM

Authors: Masao Kuriyama, Shigeru Atsumi, Ken-ichi Imamiya, Yumiko Iyama, Naohiro Matsukawa, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Sumio Tanaka

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature

Authors: Hiroshi Makino, Shuichi Matsue, Minoru Noda, Noriyuki Tanino, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

Authors: Jito Miyake, Todhinoti Maeda, Yoshito Nishimichi, Johi Katsura, Takashi Taniguchi, Seihi Yamaguchi, Hisakazu Edamatsu, Shigeru Watari, Yoshiyuko Takagi, Kazuhiko Tsuji, Shigeo Kuninobu, Steve Cox, Douglas Duschatko, Douglas MacGregor

A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM

Authors: Masato Motomura, Jun Toyoura, Kazumi Hirata, Hideyuki Ooka, Hachiro Yamada, Tadayoshi Enomoto

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

Authors: Takayuki Ootani, Shigeyuki Hayakawa, Masakazu Kakumu, Akira Aona, Masaaki Kinugawa, Hideki Takeuchi, Kazuhiro Noguchi, Tomoaki Yabe, Katsuhiko Sato, Kenji Maeguchi, Kiyofumi Ochii

A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current

Authors: Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwake, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, Osamu Minato

An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

Authors: Koichi Seki, Hitoshi Kume, Yuzuru Ohji, Takashi Kobayashi, Atushi Hiraiwa, Takeshi Nishida, Takeshi Wada, Kazuhiro Komori, Kazuto Izawa, Toshiaki Nishimoto, Yasuroh Kubota, Kazuyoshi Shoji

A 5-ns 1-Mb ECL BiCMOS SRAM

Authors: Masahide Takada, Kazuyuki Nakamura, Toshio Takeshima, Koichiro Furuta, Tohru Yamazaki, Kiyotaka Imai, Susumu Ohi, Yumi Sekine, Yukio Minato, Hisamitsu Kimuto

A 4-ns BiCMOS translation-lookaside buffer

Authors: Leilani R. Tamura, Tsen-Shau Yang, Drew E. Wingard, Mark A. Horowitz, Bruce A. Wolley

A 250-Mb/s 32*32 CMOS crosspoint LSI for ATM switching systems

Authors: Masao Akata, Shun-Ichi Karube, Takashi Sakamoto, Tadashi Saito, Shinji Yoshida, Toshio Maeda

12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technology

Authors: Haruhiko Ichino, Noboru Ishihara, Yoshiki Yamauchi, Osaake Nakajima, Koichi Nagata, Takumi Nittono

An 8-b Josephson digital signal processor

Authors: Seigo Kotani, Atsuki Inoue, Takeshi Imamura, Shinya Hasuo

An image signal multiprocessor on a single chip

Authors: Masakatsu Maruyama, Hiroyuki Nakahira, Toshiyuki Araki, Shiro Sakiyama, Yoshitaka Kitao, Kunitoshi Aono, Haruyasu Yamada

A 24-b 50-ns digital image signal processor

Authors: Shin-ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shuichi Kato, Masahiro Hatanaka, Hideo Ohira, Yoshiaki Kato, Mamoru Iwatsuki, Kinya Tabuchi, Yasutaka Horiba

An 8-b 800-MHz DAC

Authors: Kazuhisa Nojima and Yuji Gendai

A single-chip CMOS analog/digital mixed NTSC decoder

Authors: Mitsuhiko Ohta, Kiyoshi Kohiyama, Noriaki Tahara, Koi Sugihara, Fumitaka Asami, Osamu Kobayashi, Yoji Hino, Toshihiko Akiba

Simulation of mixed switched-capacitor/digital networks with signal-driven switches

Authors: Ken Suyama, San-Chin Fang, Yannis P. Tsividis

A 30-MHz mixed analog/digital signal processor

Authors: Sumitaka Takeuchi, Hiroyuki Kouno, Yoshinori Hayashi, Atsushi Maeda, Keisuke Okada, Nobuharu Yazawa

Simple noise model and low-noise data-output buffer for ultrahigh-speed memories

Authors: Tomohisa Wada, Masanao Eino, Kenji Anami

A 100-MHz 64-tap FIR digital filter in 0.8- mu m BiCMOS gate array

Authors: Toshiaki Yoshino, Rajeev Jain, Paul T. Yang, Harvey Davis, Wanda Gass, Ashwin Shah

This list is based on the data extracted from dblp: IEEE J. Solid State Circuits

Broadband ISDN ATM layer management: operations, administration, and maintenance considerations

Author: Susumu Yoneda

Hierarchical and distributed information handling for UPT

Authors: Masanobu Fujioka, Seiichiro Sakai, Hikaru Yagi

This list is based on the data extracted from dblp: IEEE Netw.

Design of IIR digital filters with arbitrary log magnitude function by WLS techniques

Authors: Takao Kobayashi and Satoshi Imai

An application of a BIC-type method to harmonic analysis and a new criterion for order determination of an AR process

Author: Hideaki Sakai

A design method for a periodically time-varying digital filter for spectrum scrambling

Authors: Ryohei Ishii and M. Kakishita

Adaptive estimation of time-varying model order in the ARMA speech analysis

Author: Hiroyoshi Morikawa

A fast adaptive filter algorithm using eigenvalue reciprocals as stepsizes

Authors: Jinhui Chao, Hctor Manuel Prez Meana, Shigeo Tsujii

Synthesis of 2-D state-space digital filters with low sensitivity based on the Fornasini-Marchesini model

Authors: Takao Hinamoto, Takashi Hamanaka, Sadao Maekawa

This list is based on the data extracted from dblp: IEEE Trans. Acoust. Speech Signal Process.

New tetrapolar circuit method using magnetic field for measurement of local impedance change in biological substances

Authors: Tadashi Takemae, Yuhio Kosugi, Haruo Saito, Jun Ikebe, Shinchi Okubo, Minoru Hongo

Left atrial pressure controller design for an artificial heart

Author: Tadashi Kitamura

Development of an implantable motor-driven assist pump system

Authors: Yoyhinodi Mitamura, Eiji Okamoto, Atsushi Hirano, Tomohisa Mikami

A method for real-time processing to study recovery functions of evoked potentials

Authors: Masatoshi Nakamura, Hiroshi Shibasaki, Shigeto Nishida, Ryuji Neshige

Three-dimensional quantitative coronary angiography

Authors: Tsuneo Saito, Motohide Misaki, Kunio Shirato, Tamotsu Takishima

On-line pressure estimation for a left heart assist device

Authors: Tadashi Kitamura and David R. Gross

An application of magnet and magnetic sensor: measurement system for tooth movement

Authors: Yoshiaki Yamada, Noriaki Yoshida, Kazuhide Kobayashi, Kiyotaka Yamauchi

This list is based on the data extracted from dblp: IEEE Trans. Biomed. Eng.

Probability distributions of interdeparture time and response time in multipacket CSMA/CD systems

Authors: Yutaka Matsumoto, Yutaka Takahashi, Toshiharu Hasegawa

The effects of packet size distributions on output and delay processes of CSMA/CD

Authors: Yutaka Matsumoto, Yutaka Takahashi, Toshiharu Hasegawa

Throughput and delay analysis of free access tree algorithm with minislots

Authors: Yuji Oie, Tatsuya Suda, Hideo Miyahara, Toshiharu Hasegawa

Variable rate speech coding for asynchronous transfer mode

Authors: Hiroshi Nakada and Ken-ichi Sato

Approximate performance analysis and simulation study for variable-channel-per-burst SS-TDMA

Authors: Masami Yabusaki and Shigefusa Suzuki

A concatenated coded modulation scheme for error control

Authors: Tadao Kasami, Toyoo Takata, Toru Fujiwara, Shu Lin

Optimal trunk reservation for a group with multislot traffic streams

Authors: Kokusai Oda and Yu Watanabe

Comments on 'Exact results for nonsymmetric token ring systems'

Authors: Gagan L. Choudhury and Hideaki Takagi

Broad-band ATM network architecture based on virtual paths

Authors: Ken-ichi Sato, Satoru Ohta, Ikuo Tokizawa

Error control criteria in the message transfer part of CCITT Signaling System No.7

Authors: Masanobu Fujioka, Yoshikazu Ikeda, Masamitsu Norigoe

Performance analysis of CSMA/CD networks with a buffered gateway

Authors: Yutaka Matsumoto, Yutaka Takahashi, Toshiharu Hasegawa

Performance analysis of token ring networks with a reservation priority discipline

Authors: Masayuki Murata, Kohei Shiomoto, Hideo Miyahara

An error control system with multiple-stage forward error corrections

Authors: Toyoo Takata, Toru Fujiwara, Tadao Kasami, Shu Lin

An extrapolative-interpolative prediction coding method for HDTV signals

Authors: Yoshiyuki Yashima and Katsutoshi Sawada

Optimal queueing discipline for real-time traffic at ATM switching nodes

Author: Hiroshi Saito

This list is based on the data extracted from dblp: IEEE Trans. Commun.

Crossing Minimization in Linear Embeddings of Graphs

Authors: Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa

Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets

Authors: Meiliu Lu, Du Zhang, Tadao Murata

Computational Complexity of Controllability/Observability Problems for Combinational Circuits

Author: Hideo Fujiwara

Fuzzy Multiple-Input Maximum and Minimum Circuits in Current Mode and Their Analyses Using Bounded-Difference Equations

Authors: Mamoru Sasaki, Takahiro Inoue, Yuji Shirai, Fumio Ueno

(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations

Authors: Hideharu Amano, Taisuke Boku, Tomohiro Kudoh

Performance Analysis of a Message-Oriented Knowledge-Base

Authors: Wang-Chan Wong, Tatsuya Suda, Lubomir Bic

This list is based on the data extracted from dblp: IEEE Trans. Computers

Optimal authentication systems and combinatorial designs

Authors: Masakazu Jimbo and Ryoh Fuji-Hara

A fast signature scheme based on congruential polynomial operations

Author: Tatsuaki Okamoto

On graphs in which the Shannon capacity is unachievable by finite product

Authors: Feng Guo and Yoichiro Watanabe

Some new binary codes correcting asymmetric/unidirectional errors

Authors: Yuichi Saitoh, Kazuhiko Yamaguchi, Hideki Imai

Error probability for digital transmission over nonlinear channels with application to TCM

Authors: Yow-Jong Liu, Ikuo Oka, Ezio Biglieri

This list is based on the data extracted from dblp: IEEE Trans. Inf. Theory

ATM communications network control by neural networks

Author: Atsushi Hiramatsu

A parallel algorithm for tiling problems

Authors: Yoshiyasu Takefuji and Kuo Chun Lee

Parallel algorithms for finding a near-maximum independent set of a circle graph

Authors: Yoshiyasu Takefuji, Li-Lin Chen, Kuo Chun Lee, John Huffman

This list is based on the data extracted from dblp: IEEE Trans. Neural Networks

A Resilient Mutual Exclusion Algorithm for Computer Networks

Authors: Shojiro Nishio, Kin F. Li, Eric G. Manning

This list is based on the data extracted from dblp: IEEE Trans. Parallel Distributed Syst.

Reconstruction of 3-D road geometry from images for autonomous land vehicles

Authors: Kenichi Kanatani and Kazunari Watanabe

Motion control of a robot arm using joint torque sensors

Authors: Kazuhiro Kosuge, H. Takeuchi, Katsuhisa Furuta

Base parameters of manipulator dynamic models

Authors: Hirokazu Mayeda, Koji Yoshida, Koichi Osuka

On a new torque sensor for tendon drive fingers

Authors: Makoto Kaneko, Kazuhito Yokoi, Kazuo Tanie

Determining shape and reflectance of hybrid surfaces by photometric sampling

Authors: Shree K. Nayar, Katsushi Ikeuchi, Takeo Kanade

This list is based on the data extracted from dblp: IEEE Trans. Robotics Autom.

Recent advances in VLSI layout

Authors: Ernest S. Kuh and Tatsuo Ohtsuki

Partial realization of 2-D discrete linear system and 2-D Pade approximation and reduction of 2-D rational transfer function

Author: Shojiro Sakata

Satellite communications systems and technology, circa 2000

Authors: S. Joseph Campanella, John V. Evans, Takuro Muratani, Pierre Bartholom

Satellite direct broadcast

Authors: Wilbur L. Pritchard and Mutsuo Ogata

Mathematical foundations of neurocomputing

Author: Shun-ichi Amari

This list is based on the data extracted from dblp: Proc. IEEE