## Highly contributed researchers

### In recent 10 years: __Kazuteru Namba__ (7)

__Nozomu Togawa__ (5) / __Nei Kato__ (5) / __Naofumi Homma__ (4)

### Since 1957: __Hideo Fujiwara__ (18) / __Tsutomu Sasao__ (18)

__Kozo Kinoshita__ (16) / __Naofumi Takagi__ (15) / __Shuzo Yajima__ (13)

## Statistics

### Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines

Authors: Tatsuhiko Shirai and Nozomu Togawa

### Multi-Spin-Flip Engineering in an Ising Machine

Authors: Tatsuhiko Shirai and Nozomu Togawa

### R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training

Authors: Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa

### VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks

Authors: Tianchen Wang, Jiawei Zhang, Jinjun Xiong, Song Bian, Zheyu Yan, Meiping Huang, Jian Zhuang, Takashi Sato, Xiaowei Xu, Yiyu Shi

### Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances

Authors: Yuta Atobe, Masashi Tawada, Nozomu Togawa

### Enabling Homomorphically Encrypted Inference for Large DNN Models

Authors: Guillermo Lloret-Talavera, Marc Jord, Harald Servat, Fabian Boemer, Chetan Chauhan, Shigeki Tomishima, Nilesh N. Shah, Antonio J. Pea

### PyQUBO: Python Library for Mapping Combinatorial Optimization Problems to QUBO Form

Authors: Mashiyat Zaman, Kotaro Tanahashi, Shu Tanaka

### How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins

Authors: Daisuke Oku, Masashi Tawada, Shu Tanaka, Nozomu Togawa

### OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives

Authors: Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi

### A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices

Authors: Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani

### High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Authors: Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger

### Footprint-Based DIMM Hotplug

Authors: Shinobu Miwa, Masaya Ishihara, Hayato Yamaki, Hiroki Honda, Martin Schulz

### Improved Division Property Based Cube Attacks Exploiting Algebraic Properties of Superpoly

Authors: Yonglin Hao, Takanori Isobe, Lin Jiao, Chaoyun Li, Willi Meier, Yosuke Todo, Qingju Wang

### An Absorbing Markov Chain Based Model to Solve Computation and Communication Tradeoff in GPU-Accelerated MDRUs for Safety Confirmation in Disaster Scenarios

Authors: Bomin Mao, Fengxiao Tang, Zubair Md. Fadlullah, Nei Kato

### Concurrent Error Detectable Carry Select Adder with Easy Testability

Authors: Nobutaka Kito and Naofumi Takagi

### Tackling Biased PUFs Through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor

Authors: Rei Ueno, Manami Suzuki, Naofumi Homma

### Value Iteration Architecture Based Deep Learning for Intelligent Routing Exploiting Heterogeneous Computing Platforms

Authors: Zubair Md. Fadlullah, Bomin Mao, Fengxiao Tang, Nei Kato

### Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)

Authors: Kazuteru Namba and Fabrizio Lombardi

### Cube Attacks on Non-Blackbox Polynomials Based on Division Property

Authors: Yosuke Todo, Takanori Isobe, Yonglin Hao, Willi Meier

### A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits

Authors: Kazuteru Namba and Fabrizio Lombardi

### Cloudlets Activation Scheme for Scalable Mobile Edge Computing with Transmission Power Control and Virtual Machine Migration

Authors: Tiago Gama Rodrigues, Katsuya Suto, Hiroki Nishiyama, Nei Kato, Katsuhiro Temma

### Tight Bounds of Differentially and Linearly Active S-Boxes and Division Property of Lilliput

Authors: Yu Sasaki and Yosuke Todo

### Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory

Authors: Hiroshi Uchigaito, Seiji Miura, Takumi Nito

### Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM

Authors: Masahiro Ishii, Jrmie Detrey, Pierrick Gaudry, Atsuo Inomata, Kazutoshi Fujikawa

### Routing or Computing? The Paradigm Shift Towards Intelligent Computer Network Packet Transmission Based on Deep Learning

Authors: Bomin Mao, Zubair Md. Fadlullah, Fengxiao Tang, Nei Kato, Osamu Akashi, Takeru Inoue, Kimihiro Mizutani

### Hybrid Method for Minimizing Service Delay in Edge Cloud Computing Through VM Migration and Transmission Power Control

Authors: Tiago Gama Rodrigues, Katsuya Suto, Hiroki Nishiyama, Nei Kato

### Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Authors: Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

### Formal Approach for Verifying Galois Field Arithmetic Circuits of Higher Degrees

Authors: Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Takafumi Aoki

### Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems

Authors: Kazuteru Namba and Fabrizio Lombardi

### Disaggregation and Sharing of I/O Devices in Cloud Data Centers

Authors: Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Yuki Hayashi, Masaki Kan, Takashi Yoshikawa

### GPUvm: GPU Virtualization at the Hypervisor

Authors: Yusuke Suzuki, Shinpei Kato, Hiroshi Yamada, Kenji Kono

### Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip

Authors: Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara

### Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems

Authors: Kazuteru Namba and Fabrizio Lombardi

### A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

Authors: Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi

### A Novel Coding Scheme for Secure Communications in Distributed RFID Systems

Authors: Kazuya Sakai, Min-Te Sun, Wei-Shinn Ku, Ten-Hwang Lai

### Energy Minimization in Multi-Task Software-Defined Sensor Networks

Authors: Deze Zeng, Peng Li, Song Guo, Toshiaki Miyazaki, Jiankun Hu, Yong Xiang

### Parallel Decodable Two-Level Unequal Burst Error Correcting Codes

Authors: Kazuteru Namba and Fabrizio Lombardi

### Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)

Authors: Kazuteru Namba and Fabrizio Lombardi

### Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition

Authors: Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi

### Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs

Authors: Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume, Jiann-Liang Chen

### Software Implementation of an Attribute-Based Encryption Scheme

Authors: Eric Zavattoni, Luis J. Dominguez Perez, Shigeo Mitsunari, Ana H. Snchez-Ramrez, Tadanori Teruya, Francisco Rodrguez-Henrquez

### Toward Formal Design of Practical Cryptographic Hardware Based on Galois Field Arithmetic

Authors: Naofumi Homma, Kazuya Saito, Takafumi Aoki

### High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

Authors: Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu

### 3D NoC with Inductive-Coupling Links for Building-Block SiPs

Authors: Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano

### Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators

Authors: Sagi Manole, Amit Golander, Shlomo Weiss

### Dynamic Bit Encoding for Privacy Protection against Correlation Attacks in RFID Backward Channel

Authors: Kazuya Sakai, Wei-Shinn Ku, Roger Zimmermann, Min-Te Sun

### Enhancing Performance of Random Testing through Markov Chain Monte Carlo Methods

Authors: Bo Zhou, Hiroyuki Okamura, Tadashi Dohi

### Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits

Authors: Kazuteru Namba and Hideo Ito

### A Branch-and-Bound Algorithm for Solving the Multiprocessor Scheduling Problem with Improved Lower Bounding Techniques

Author: Satoshi Fujita

### Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Authors: Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga

### Fast Architectures for the \eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves

Authors: Jean-Luc Beuchat, Jrmie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodrguez-Henrquez

### Stability-Optimized Time Adjustment for a Networked Computer Clock

Author: Takao Yamashita

### Comparative Power Analysis of Modular Exponentiation Algorithms

Authors: Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir

### Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement

Authors: Hao Zheng, Haiqiong Yao, Tomohiro Yoneda

### Orchestrating Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency

Authors: Hai Lin and Yunsi Fei

### High-Performance Hardware Architectures for Galois Counter Mode

Authors: Akashi Satoh, Takeshi Sugawara, Takafumi Aoki

### Complexities of Graph-Based Representations for Elementary Functions

Authors: Shinobu Nagayama and Tsutomu Sasao

### A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams

Authors: Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

### Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three

Authors: Jean-Luc Beuchat, Nicolas Brisebarre, Jrmie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi

### Elliptic-Curve-Based Security Processor for RFID

Authors: Yong Ki Lee, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede

### A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

Authors: rika F. Cota, Fernanda Gusmo de Lima Kastensmidt, Maico Cassel, Marcos Herv, Pedro Almeida, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski

### Short-Memory Scalar Multiplication for Koblitz Curves

Authors: Camille Vuillaume, Katsuyuki Okeya, Tsuyoshi Takagi

### Bipartite Modular Multiplication Method

Authors: Marcelo E. Kaihara and Naofumi Takagi

### Communication Links for Distributed Quantum Computation

Authors: Rodney Van Meter, Kae Nemoto, W. J. Munro

### Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

Authors: Dong Xiang, Mingjing Chen, Hideo Fujiwara

### Guest Editors' Introduction: Special Section on Emergent Systems, Algorithms and Architectures for Speech-Based Human-Machine Interaction

Authors: Rodrigo Capobianco Guido, Li Deng, Shoji Makino

### Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n)

Authors: Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede

### Incorporating Knowledge Sources Into a Statistical Acoustic Model for Spoken Language Communication Systems

Authors: Sakriani Sakti, Konstantin Markov, Satoshi Nakamura

### Numerical Function Generators Using LUT Cascades

Authors: Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler

### An Integrated Memory Array Processor for Embedded Image Recognition Systems

Authors: Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai

### Modified Low-Density MDS Array Codes for Tolerating Double Disk Failures in Disk Arrays

Authors: Hachiro Fujita and Kohichi Sakaniwa

### Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction

Authors: Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara

### Adaptive Resource Allocation Control for Fair QoS Management

Authors: Fumiko Harada, Toshimitsu Ushio, Yukikazu Nakamoto

### On the Prediction of Java Object Lifetimes

Authors: Hajime Inoue, Darko Stefanovic, Stephanie Forrest

### Condition Adaptation in Synchronous Consensus

Authors: Taisuke Izumi and Toshimitsu Masuzawa

### Analysis of Fractional Window Recoding Methods and Their Application to Elliptic Curve Cryptosystems

Authors: Katja Schmidt-Samoa, Olivier Semay, Tsuyoshi Takagi

### Average Path Length of Binary Decision Diagrams

Authors: Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura

### Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages

Authors: Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama

### A Hardware Algorithm for Modular Multiplication/Division

Authors: Marcelo E. Kaihara and Naofumi Takagi

### Parallel Decoding Cyclic Burst Error Correcting Codes

Authors: Ganesan Umanesan and Eiji Fujiwara

### A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems

Authors: Mahmoud Mribout and Masato Motomura

### Virtualizing Network I/O on End-Host Operating System: Operating System Support forNetwork Control and Resource Protection

Authors: Takashi Okumura and Daniel Moss

### Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines

Authors: Jia Lee, Ferdinand Peper, Susumu Adachi, Kenichi Morita

### A General Stochastic Model for Dynamic Locking in Database Systems

Authors: Yong Jiang, Jie Li, Shoichi Nishimura

### A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices

Authors: Haruhiko Kaneko and Eiji Fujiwara

### Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution

Authors: Dong Xiang, Yi Xu, Hideo Fujiwara

### (t, k)-Diagnosable System: A Generalization of the PMC Models

Authors: Toru Araki and Yukio Shibata

### A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes

Authors: Ganesan Umanesan and Eiji Fujiwara

### A Scalable Dual-Field Elliptic Curve Cryptographic Processor

Authors: Akashi Satoh and Kohji Takano

### Streaming BDD Manipulation

Author: Shin-ichi Minato

### A Method for Compressing Test Data Based on Burrows-Wheeler Transformation

Authors: Takahiro J. Yamaguchi, Dong Sam Ha, Masahiro Ishida, Tadahiro Ohmi

### ROC-1: Hardware Support for Recovery-Oriented Computing

Authors: David L. Oppenheimer, Aaron B. Brown, James Beck, Daniel Hettena, Jon Kuroda, Noah Treuhaft, David A. Patterson, Katherine A. Yelick

### A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs

Authors: Jawahar Jain, Ingo Wegener, Masahiro Fujita

### Lookahead Scheduling Requests for Multisize Page Caching

Authors: Jun Kiniwa, Toshio Hamada, Daisuke Mizoguchi

### Worst and Best Irredundant Sum-of-Products Expressions

Authors: Tsutomu Sasao and Jon T. Butler

### A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis

Authors: Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi

### Neighborhood Information Dissemination in the Star Graph

Author: Satoshi Fujita

### RT-CRM: Real-Time Channel-Based Reflective Memory

Authors: Chia Shen and Ichiro Mizunuma

### A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector

Authors: Naofumi Takagi and Seiji Kuwahara

### A New Class of Sequential Circuits with Combinational Test Generation Complexity

Author: Hideo Fujiwara

### Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions

Authors: Tadayoshi Horita and Itsuo Takanami

### Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring

Author: Nobuo Tsuda

### Discrete Interval Truth Values Logic and Its Application

Authors: Noboru Takagi and Kyoichi Nakashima

### A Fault-Tolerant Broadcast Scheme in the Star Graph under the Single-Port, Half-Duplex Communication Model

Author: Satoshi Fujita

### Improving the Availability of Mutual Exclusion Systems on Incomplete Networks

Authors: Takashi Harada and Masafumi Yamashita

### The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing

Authors: Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi

### Augmenting Loop Tiling with Data Alignment for Improved Cache Performance

Authors: Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau

### A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation

Authors: Andreas Savva and Takashi Nanya

### A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival

Authors: Naofumi Takagi and Takashi Horiyama

### Improving Design Dependability by Exploiting an Open Model-Based Specification

Authors: Aki W. Tomita and Ken Sakamura

### Optimal Two-Level Unequal Error Control Codes for Computer Systems

Authors: Eiji Fujiwara, Tepparit Ritthongpitak, Masato Kitakami

### Powering by a Table Look-Up and a Multiplication with Operand Modification

Author: Naofumi Takagi

### CAM2: A Highly-Parallel Two-Dimensional Cellular Architecture

Authors: Takeshi Ikenaga and Takeshi Ogura

### Load Balancing Problems for Multiclass Jobs in Distributed/Parallel Computer Systems

Authors: Jie Li and Hisao Kameda

### A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications

Authors: Zheng Tang and Okihiko Ishizuka

### A Hierarachical Adaptive Distributed System-Level Diagnosis Algorithm

Authors: Elias Procpio Duarte Jr. and Takashi Nanya

### O(n)-Depth Modular Exponentiation Circuit Algorithm

Authors: Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata

### Easily Testable Realizations for Generalized Reed-Muller Expressions

Author: Tsutomu Sasao

### Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions

Authors: Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III

### Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification

Authors: Masayuki Ito, Naofumi Takagi, Shuzo Yajima

### A Residue Arithmetic Extension for Reliable Scientific Computation

Authors: Eisuke Kinoshita and Ki-Ja Lee

### A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-

Authors: Mitsuru Hamada and Eiji Fujiwara

### Fault-Tolerant Design of Neural Networks for Solving Optimization Problems

Authors: Yoshihiro Tohma and Yoichi Koyanagi

### Fast Gossiping on Mesh-Bus Computers

Authors: Satoshi Fujita and Masafumi Yamashita

### Author's Reply

Authors: Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

### Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers

Authors: Yooichi Shintani, Toru Shonai, Hiroshi Kurokawa, Kazunori Kuriyama, Akira Yamaoka

### Probability to Achieve TSC Goal

Authors: Jien-Chung Lo and Eiji Fujiwara

### Aliasing Error for a Mask ROM Built-In Self-Test

Authors: Kazuhiko Iwasaki and Shigeo Nakamura

### On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers

Authors: Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki

### Hypercube Multiprocessors with Bus Connections for Improving Communication Performance

Author: Tsutomu Ishikawa

### A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers

Authors: Yooichi Shintani, Kiyoshi Inoue, Eiki Kamada, Toru Shonai

### Stochastic Models for Performance Analysis of Database Recovery Control

Authors: Paulo B. Ges and Ushio Sumita

### Fast Evaluation of the Elementary Functions in Single Precision

Authors: Weng-Fai Wong and Eiichi Goto

### A Design of Reed-Solomon Decoder with Systolic Array Structure

Authors: Keiichi Iwamura, Yasunori Dohi, Hideki Imai

### On Polynomial-Time Testable Combinational Circuits

Authors: Nageswara S. V. Rao and Shunichi Toida

### A Highly OR-Parallel Inference Machine (Multi-ASCA) and Its Performance Evaluation: An Architecture and Its Load Balancing Algorithms

Authors: Jiro Naganuma and Takeshi Ogura

### Logically Instantaneous Message Passing in Asynchronous Distributed Systems

Authors: Terunao Soneoka and Toshihide Ibaraki

### Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers

Authors: Weng-Fai Wong and Eiichi Goto

### Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation

Authors: Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu

### High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits

Authors: Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

### A Note on Aliasing Probability for Multiple Input Signature Analyzer

Authors: Masakatu Morii and Kazuhiko Iwasaki

### Some Fundamental Properties of Multiple-Valued Kleenean Functions and Determination of Their Logic Formulas

Authors: Yutaka Hata, Kyoichi Nakashima, Kazuharu Yamato

### Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors

Authors: Kishore Kota and Joseph R. Cavallaro

### Minimization of AND-EXOR Expressions Using Rewrite Rules

Authors: Daniel Brand and Tsutomu Sasao

### Availability of k-Coterie

Authors: Hirotsugu Kakugawa, Satoshi Fujita, Masafumi Yamashita, Tadashi Ae

### Some Codes for Correcting and Detecting Unidirectional Byte Errors

Authors: Yuichi Saitoh and Hideki Imai

### Comparisons of Seven Neural Network Models on Traffic Control Problems in Multistage Interconnection Networks

Authors: Nobuo Funabiki, Yoshiyasu Takefuji, Kuo Chun Lee

### Notes on Multiple Input Signature Analysis

Authors: Tiko Kameda, Slawomir Pilarski, Andr Ivanov

### Task Allocation for Maximizing Reliability of Distributed Computer Systems

Authors: Sol M. Shatz, Jia-Ping Wang, Masanori Goto

### A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation

Author: Naofumi Takagi

### Overflow/Underflow-Free Floating-Point Number Representations with Self-Delimiting Variable-Length Exponent Field

Author: Hidetoshi Yokoo

### Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem

Authors: Naofumi Takagi and Shuzo Yajima

### Cache Memories for Data Flow Machines

Author: Masaru Takesue

### A Testable Design of Logic Circuits under Highly Observable Condition

Authors: Xiaoqing Wen and Kozo Kinoshita

### P-Functions-Ternary Logic Functions Capable of Correcting Input Failures and Suitable for Treating Ambiguities

Authors: Yoshinori Yamamoto and Masao Mukaidono

### Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation

Authors: Naofumi Takagi, Tohru Asada, Shuzo Yajima

### Pseudorandom Rounding for Truncated Multipliers

Authors: Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa

### A Note on t-Unidirectional Error Correcting and d(d=t)-Unidirectional Error Detecting (t-UEC and d-UED) Codes

Authors: Kohichi Sakaniwa, Tae Nam Ahn, T. R. N. Rao

### Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions

Author: Tsutomu Sasao

### SDE: Incremental Specification and Development of Communications Software

Authors: Haruhisa Ichikawa, Masaki Itoh, June Kato, Akira Takura, Masashi Shibasaki

### An Integrated Approach to Design of Protocol Specifications Using Protocol Validation and Synthesis

Authors: Yoshiaki Kakuda and Hironori Saito

### Strategic Testing Environment with Formal Description Techniques

Authors: Kotaro Katsuyama, Fumiaki Sato, Tetsuo Nakakawaji, Tadanori Mizuno

### A User Friendly Software Environment for Protocol Synthesis

Authors: Norio Shiratori, Yaoxue Zhang, Kaoru Takahashi, Shoichi Noguchi

### (SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations

Authors: Hideharu Amano, Taisuke Boku, Tomohiro Kudoh

### Computational Complexity of Controllability/Observability Problems for Combinational Circuits

Author: Hideo Fujiwara

### Fuzzy Multiple-Input Maximum and Minimum Circuits in Current Mode and Their Analyses Using Bounded-Difference Equations

Authors: Mamoru Sasaki, Takahiro Inoue, Yuji Shirai, Fumio Ueno

### Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets

Authors: Meiliu Lu, Du Zhang, Tadao Murata

### Crossing Minimization in Linear Embeddings of Graphs

Authors: Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa

### The Via Minimization Problem is NP-Complete

Authors: Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima

### The Transduction Method-Design of Logic Networks Based on Permissible Functions

Authors: Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney

### The CrossoverNet LAN System Using an Intelligent Head-End

Authors: Senro Saito, Hiroyuki Yoshida, Tosiyasu L. Kunii

### An Adaptive Hierarchical Routing Protocol

Authors: Wei-Tek Tsai, C. V. Ramamoorthy, Wei Kang Tsai, Osamu Nishiguchi

### The Stack Growth Function: Cache Line Reference Models

Authors: Makoto Kobayashi and Myron H. MacDougall

### CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines

Authors: Kentaro Shimizu, Eiichi Goto, Shuichi Ichikawa

### Tolerance of Double-Loop Computer Networks to Multinode Failures

Authors: Hiroshi Masuyama and Tetsuo Ichimori

### Temporal Petri Nets and Their Application to Modeling and Analysis of a Handshake Daisy Chain Arbiter

Authors: Ichiro Suzuki and Harngdar Lu

### On the Optimal Design of Multiple-Valued PLA's

Author: Tsutomu Sasao

### K-Way Bitonic Sort

Authors: Toshio Nakatani, Shing-Tsaan Huang, Bruce W. Arden, Satish K. Tripathi

### Criteria for Selecting a Variable in the Construction of Efficient Decision Trees

Author: Masahiro Miyakawa

### High-Speed CAM-Based Architecture for a Prolog Machine (ASCA)

Authors: Jiro Naganuma, Takeshi Ogura, Shin-Ichiro Yamada, Takashi Kimura

### Relationship Between P-Valued Majority Functions and P-Valued Threshold Functions

Authors: Yoshinori Yamamoto and Shiro Fujita

### Meaningful Special Classes of Ternary Logic Functions - Regular Ternary Logic Functions and Ternary Majority Functions

Authors: Yoshinori Yamamoto and Masao Mukaidono

### Equilibrium Point Analysis of Memory Interference in Multiprocessor Systems

Author: Akira Fukuda

### A Single Chip Parallel Multiplier by MOS Technology

Authors: Shinji Nakamura and Kai-Yu Chu

### Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors

Authors: Takashi Nanya and Toshiaki Kawamura

### On Error Indication for Totally Self-Checking Systems

Authors: Takashi Nanya and Toshiaki Kawamura

### On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic

Authors: Naofumi Takagi and Shuzo Yajima

### A Construction Method of High-Speed Decoders Using ROMS's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon Codes

Authors: Hirokazu Okano and Hideki Imai

### A Note on Strongly Fault-Secure Sequential Circuits

Authors: Takashi Nanya and Toshiaki Kawamura

### Binary Search Revisited: Another Advantage of Fibonacci Search

Authors: Seiichi Nishihara and Hiroji Nishino

### New Methods for Realizing Plural Near-Native Performance Virtual Machines

Authors: Hidenori Umeno and Shunji Tanaka

### Asignment of Job Modules onto Array Processors

Authors: Kunio Fukunaga, Shoichiro Yamada, Tamotsu Kasai

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