IEEE Journals & Magazines 1991 Papers Published by Researchers in Japan in 1991

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Highly contributed researchers in 1991

Shoichi Noguchi (5) / Kiyoo Itoh (5)

IEEE Communications Magazine

Universal service creation and provision environment for intelligent network

Authors: Masanobu Fujioka, Hikaru Yagi, Yoshikazu Ikeda

A concurrent object-oriented switching program in Chill

Authors: Katsumi Maruyama, Nobuyuki Watanabe, Keiich Koyanagi, Toshihiro Kai, Shuji Tomita

Large-scale ATM multistage switching network with shared buffer memory switches

Authors: Yoshito Sakurai, Nobuhiko Ido, Shinobu Gohara, Noboru Endo

Japanese subscriber loop network and fiber optic loop development

Authors: Tetsuya Miki and Ryoichi Komiya

Construction aspects of intelligent buildings

Authors: Sumio Fujie and Yuji Mikami

Telecommunications aspects of intelligent buildings

Authors: Takao Kashiwamura, Hisao Koga, Yasuji Murakami

HDTV communication systems in broadband communication networks

Authors: Ryozo Kishimoto and Ichiro Yamashita

HDTV broadcasting systems

Author: Yuichi Ninomiya

Traffic control in asynchronous transfer mode

Authors: Tadanobu Okada, Hirokazu Ohnishi, Naotaka Morita

Implementation of coded modems

Authors: Shuzo Kato, Masahiro Morikura, Shuji Kubota

Multi-h phase-coded modulation

Authors: Iwao Sasase and Shinsaku Mori

This list is based on the data extracted from dblp: IEEE Communications Magazine

IEEE J. Sel. Areas Communications

Computer-Aided Planning of SS/TDMA Network Operation

Authors: Takeshi Mizuike, Yasuhiko Ito, Lan N. Nguyen, Eijiro Maeda

Virtual Path and Link Capacity Design for ATM Networks

Authors: Youichi Sato and Ken-ichi Sato

Switched Batch Bernoulli Process (SBBP) and the Discrete-Time SBBP/G/1 Queue with Application to Statistical Multiplexer Performance

Authors: On Hashida, Yoshitaka Takahashi, Shinsuke Shimogawa

Analysis of Interdeparture Processes for Bursty Traffic in ATM Networks

Authors: Yoshihiro Ohba, Masayuki Murata, Hideo Miyahara

An Analysis of Statistical Multiplexing in an ATM Transport Network

Authors: Hiroshi Saito, Masatoshi Kawarasaki, Hiroshi Yamada

A Traffic Measurement Method and its Application for Cell Loss Probability Estimation in ATM Networks

Authors: Hiroshi Yamada and Shuichi Sumita

Consideration on Three-Dimensional Visual Communication Systems

Authors: Kenji Akiyama, Nobuji Tetsutani, Morito Ishibashi, Susumu Ichinose, Hiroshi Yasuda

The Human Interface in a Multifunctional Communication Terminal

Authors: Hajime Kamata, Akihiko Obata, Motomitsu Adachi, Shuzo Morita

Pure Delay Effects on Speech Quality in Telecommunications

Authors: Nobuhiko Kitawaki and Kenzo Itoh

Forming Mental Models in Learning Operating Procedures for Terminal Equipment

Authors: Naoki Matsuo, Hiroyuki Matsui, Yukio Tokunaga

VOICE-AID: Pushbutton-to-Speech System for Vocally Handicapped People

Author: Tsutomu Miyasato

A Media Conversion from Speech to Facial Image for Intelligent Man-Machine Interface

Authors: Shigeo Morishima and Hiroshi Harashima

Distributed Desktop Conferencing System with Multiuser Multimedia Interface

Authors: Kazuo Watabe, Shiro Sakata, Kazutoshi Maeno, Hideyuki Fukuoka, Toyoko Ohmori

Over 10 Gb/s Regenarators Using Monolithic IC's for Lightwave Communication Systems

Authors: Kazuo Hagimoto, Yuuzou Miyagawa, Yutaka Miyamoto, Masanobu Ohhata, Tatsuhito Suzuki, Hiroyuki Kikuchi

High-Speed Si-Bipolar IC Design for Multi-GB/s Optical Receivers

Authors: Hiroshi Hamano, Takuji Yamamoto, Yoshinori Nishizawa, Akinori Tahara, Norihito Miyoshi, Kouichi Suzuki, Akihito Nishimura

High-Speed Optical Transmission Systems Using Advanced Monolithic IC Technologies

Authors: Kiyoshi Nakagawa and Katsushi Iwashita

A Gigabit-Rate Five-Highway GaAs OE-LSI Chipset for High-Speed Optical Interconnections Between Modules or VLSI's

Authors: Naoaki Yamanaka, Masaharu Sasaki, Shiro Kikuchi, Thoru Takada, Masao Idda

Integration of ATM Call Admission Control and Link Capacity Control by Distributed Neural Networks

Author: Atsushi Hiramatsu

Dynamic Call Admission Control in ATM Networks

Authors: Hiroshi Saito and Kohei Shiomoto

Priority Assignment Control of ATM Line Buffers with Multiple QOS Classes

Authors: Yasushi Takagi, Shigeki Hino, Tatsuro Takahashi

A Fault-Tolerant Switching Network for B-ISDN

Author: Arata Itoh

Practical Implementation and Packaging Technologies for a Large-Scale ATM Switching System

Authors: Atsuo Itoh, Wataru Takahashi, Hiroshi Nagano, Masaru Kurisaka, Susumu Iwasaki

32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's

Authors: Takahiko Kozaki, Noboru Endo, Yoshito Sakurai, Osamu Matsubara, Masao Mizukami, Ken'ichi Asano

A 1.5 Gb/s 8 X 8 Cross-Connect Switch Using a Time Reservation Algorithm

Authors: Haruhiko Matsunaga and Hitoshi Uematsu

A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture

Authors: Yasuro Shobatake, Masahiko Motoyama, Emiko Shobatake, Takashi Kamitake, Shoichi Shimizu, Makoto Noda, Kenji Sakaue

Rerouting Network: A High-Performance Self-Routing Switch for B-ISDN

Author: Shigeo Urushidani

Evaluation of the Effects of Protocol Processing Overhead in Error Recovery Schemes for a High-Speed Packet Switched Network: Link-by-Link versus Edge-to-Edge Schemes

Authors: Jaime Jungok Bae, Tatsuya Suda, Naoya Watanabe

B-ISDN Architecture and Protocol

Authors: Masatoshi Kawarasaki and Bijan Jabbari

A Call Admission Control Scheme for ATM Networks Using a Simple Quality Estimate

Authors: Tutomu Murase, Hiroshi Suzuki, Shohei Sato, Takao Takeuchi

A Cell Loss Recovery Method Using FEC in ATM Networks

Authors: Hiroshi Ohta and Tokuhiro Kitami

A Control-Ahead ATM Switch Architecture and Its Performance

Authors: Miki Yamamoto, Hideki Tode, Hiromi Okada, Yoshikazu Tezuka

This list is based on the data extracted from dblp: IEEE J. Sel. Areas Communications

IEEE J. Solid State Circuits

Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling

Authors: Minoru Fujishima, Kunihiro Asada, Takuo Sugano

A flexible redundancy technique for high-density DRAMs

Authors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh, Tetsuro Matsumoto

Power-speed product of an optical flip-flop memory with optical feedback

Authors: Kazutoshi Nakajima, Hirofumi Kan, Yoshihiko Mizushima

Variable bit organization as a new test function for standard memories

Authors: Tomohisa Wada, Masanao Eino, Motomu Ukita, Kenji Anami

A BiCMOS PLL-based data separator circuit with high stability and accuracy

Authors: Shyoichi Miyazawa, Ryutaro Horita, Kenichi Hase, Kazuo Kato, Shinichi Kojima

Delay analysis of series-connected MOSFET circuits

Authors: Takayasu Sakurai and A. Richard Newton

A 6-ns 256-kb BiCMOS TTL SRAM

Authors: Takashi Akioka, Atsushi Hiraishi, Tatsumi Yamauchi, Yuji Yokoyama, Shigeru Takahashi, Masahiro Iwamura, Yutaka Kobayashi, Akira Ide, Nobuyuki Gotou, Kazunori Onozawa, Hideaki Uchida

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates

Authors: Toshiaki Hanibuchi, Masahiro Ueda, Keiichi Higashitani, Masahiro Hatanaka, Koichiro Mashiko, Akiharu Tada

A flexible multiport RAM compiler for data path

Authors: Hirofumi Shinohara, Noriaki Matsumoto, Kumiko Fujimori, Yoshiki Tsujihashi, Hiroomi Nakao, Shuichi Kato, Yasutaka Horiba, Akiharu Tada

Hierarchical symbolic design methodology for large-scale data paths

Authors: Kimiyoshi Usami, Yukio Sugeno, Nobu Matsumoto, Shojiro Mori

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

Authors: Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano

A circuit design of intelligent cache DRAM with automatic write-back capability

Authors: Kazutami Arimoto, Mikio Asakura, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima

Fast-access BiCMOS SRAM architecture with a VSS generator

Authors: Takakuni Douseki, Yasuo Ohmori, Hideo Yoshino, Junzo Yamada

Pipelined, time-sharing access technique for an integrated multiport memory

Authors: Ken-ichi Endo, Tsuneo Matsumura, Junzo Yamada

A dynamic three-state memory cell for high-density associative processors

Authors: Frederick P. Herrmann, Craig L. Keast, Keisuke Ishio, Jon P. Wade, Charles G. Sodini

A divided/shared bit-line sensing scheme for ULSI DRAM cores

Authors: Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima

Josephson macrocell array

Authors: Seigo Kotani, Atsuki Inoue, Shinya Hasuo

PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor

Authors: Kozaburo Kurita, Takashi Hotta, Tetsuo Nakano, Nobuaki Kitamura

An 8 ns 4 Mb serial access memory

Authors: Hirotada Kuriyama, Toshihiko Hirose, Shuji Murakami, Tomohisa Wada, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami

A fully operational 1 kb variable threshold Josephson RAM

Authors: Itaru Kurosawa, Hiroshi Nakagawa, Masahiro Aoyagi, Shin Kosaka, Susumu Takada

A 12 MHz data cycle 4 Mb DRAM with pipeline operation

Authors: Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama, Tohru Furuyama

A highly sensitive on-chip charge detector for CCD area image sensor

Authors: Yoshiyuki Matsunaga, Hirofumi Yamashita, Shinji Ohsawa

100-MHz serial access architecture for 4-Mb field memory

Authors: Mayu Miyauchi, Hiroaki Ikeda, Akira Tsujimoto, Yoshinori Sato, Junji Tajima, Takao Adachi, Kunihiro Hamaguchi, Naohiro Fukuhara

A 4 Mb NAND EEPROM with tight programmed Vt distribution

Authors: Masaki Momodomi, Tomoharu Tanaka, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

Authors: Junji Mori, Masato Nagamatsu, Masashi Hirano, Shigeru Tanaka, Makoto Noda, Yoshiaki Toyoshima, Kazuhiro Hashimoto, Hiroyuki Hayashida, Kenji Maeguchi

An experimental 1.5-V 64-Mb DRAM

Authors: Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh

A 10-b 70-MS/s CMOS D/A converter

Authors: Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh, Nobuharu Yazawa

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

Authors: Yasunobu Nakase, Kakutaro Suda, Koichiro Mashiko, Tatsuhiko Ikeda, Shinpei Kayano

A 1 Mb EEPROM with MONOS memory cell for semiconductor disk application

Authors: Takaaki Nozaki, Toshiaki Tanaka, Yoshiro Kijiya, Eita Kinoshita, Tatsuo Tsuchiya, Yutaka Hayashi

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

Authors: Atsushi Ohba, Shigeki Ohbayashi, Toru Shiomi, Satoshi Takano, Kenji Anami, Hiroki Honda, Yoshiyuki Ishigaki, Masahiro Hatanaka, Shigeo Nagao, Shimpei Kayano

100-MHz monolithic low-pass filters with transmission zeros using NIC integrators

Authors: Shigetaka Takagi, Hajime Nitta, Jorge Koyama, Makoto Furihata, Nobuo Fujii, Minoru Nagata, Takeshi Yanagisawa

Design of a second-level cache chip for shared-bus multimicroprocessor systems

Authors: Kunio Uchiyama, Hirokazu Aoki, Osamu Nishii, Susumu Hatano, Osamu Nagashima, Kanji Oishi, Jun Kitano

High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic

Authors: Hans J. Greub, John F. McDonald, Ted Creedon, Tadanori Yamaguchi

An active resistor network for Gaussian filtering of images

Authors: Haruo Kobayashi, Joseph L. White, Asad A. Abidi

A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array

Authors: Tai-ichi Otsuji and Naoaki Narumi

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM

Authors: Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki

Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled pairs

Authors: Hiroshi Tanimoto, Mikio Koyama, Yoshihiro Yoshida

Comments on 18-GHz 1/8 dynamic frequency divider using Si bipolar technologies (and reply)

Authors: Rainer H. Derksen and Haruhiko Ichino

An all DC-powered Josephson logic circuit

Authors: Yuji Hatano, Hideyuki Nagaishi, Shinichiro Yano, Kouji Nakahara, Hiroji Yamada, Shinya Kominami, Mikio Hirano

A new MOS imager using photodiode as current source

Author: Mikio Kyomasu

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network

Authors: Kenji Sakaue, Yasuro Shobatake, Masahiko Motoyama, Yoshinari Kumaki, Satoru Takatsuka, Shigeru Tanaka, Hiroyuki Hara, Kouji Matsuda, Shuji Kitaoka, Makoto Noda, Youichiro Niitsu, Masayuki Norishima, Hiroshi Momose, Kenji Maeguchi, Manabu Ishibe, Shoichi Shimizu, Toshikazu Kodama

An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate

Authors: Yoshito Nejime, Masao Hotta, Seiichi Ueda

Ultrahigh-speed HEMT LSI technology for supercomputer

Authors: Masayuki Abe and Takashi Mimura

10 K-gate GaAs JFET sea of gates

Authors: Hidetoshi Kawasaki, Masaru Wada, Yukio Hida, Chiaki Takano, Jiro Kasahara

A 5-ns GaAs 16-kb SRAM

Authors: Shuichi Matsue, Hiroshi Makino, Minoru Noda, Hirofumi Nakano, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano

Multipurpose high-coding-gain 0.8- mu m BiCMOS VLSIs for high-speed multilevel trellis-coded modulation

Authors: Satoru Aikawa, Yasuhisa Nakamura, Hitoshi Takanashi

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture

Authors: Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano

0.5- mu m 2 M-transistor BiPNMOS channelless gate array

Authors: Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test

Authors: Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Gyoo Itoh, Kazuhiko Kajigaya, Atsushi Nozoe, Tetsuro Matsumoto

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAMs

Authors: Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh

Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond

Authors: Shigeru Kikuda, Hiroshi Miyamoto, Shigeru Mori, Mitsutaka Niiro, Michihiro Yamada

A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture

Authors: Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto

A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation

Authors: Tsuguo Kobayashi, Kazutaka Nogami, Tsukasa Shirotori, Yukihiro Fujimoto, Yoshitaka Biwaki, Haruo Nohara, Makiji Kobayashi, Kiyoshi Kobayashi, Kazuhiro Sawada

A Si bipolar 21-GHz/320-mW static frequency divider

Authors: Masakazu Kurisu, Masahiro Ohuchi, Akihiro Sawairi, Mitsuhiro Sugiyama, Hisashi Takemura, Tsutomu Tashiro

A 45-ns 64-Mb DRAM with a merged match-line test architecture

Authors: Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

A 21-mW 4-Mb CMOS SRAM for battery operation

Authors: Shuji Murakami, Kore-aki Fujita, Motomu Ukita, Kazuhito Tsutsumi, Yasuo Inoue, Osamu Sakamoto, Motoi Ashida, Yasumasa Nishimura, Yoshio Kohno, Tadashi Nishimura, Kenji Anami

A 17-ns 4-Mb CMOS DRAM

Authors: Takeshi Nagai, Kenji Numata, Masaki Ogihara, Mitsuru Shimizu, Kimimasa Imai, Takahiko Hara, Munehiro Yoshida, Yoshikazu Saito, Yoshiaki Asao, Shizuo Sawada, Syuso Fujii

An intelligent subprocessor for hardware emulation with 20-MOPS performance

Authors: Hideo Nakamura, Terumi Sawase, Yasushi Akao, Shigeki Masumura, Makoto Hayashi, Hiroshi Ohsuga, Yuji Satoh, Tatsuya Aizawa

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

Authors: Takeshi Nakayama, Shin'ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki

A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates

Authors: Seishi Notomi, Yuu Watanabe, Makoto Kosugi, Isamu Hanyu, Masahisa Suzuki, Takashi Mimura, Masayuki Abe

A 33-ns 64-Mb DRAM

Authors: Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka

A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current

Authors: Katsuyuki Sato, Kanehide Kenmizaki, Shoji Kubono, Toshio Mochizuki, Hidetomo Aoyagi, Michitaro Kanamitsu, Soichi Kunito, Hiroyuki Uchida, Yoshihiko Yasu, Atsushi Ogishima, Sho Sano, Hiroshi Kawamoto

A 1.2-ns HEMT 64-kb SRAM

Authors: Masahisa Suzuki, Seishi Notomi, Masaaki Ono, Naoki Kobayashi, Eizo Mitani, Kouichiro Odani, Takashi Mimura, Masayuki Abe

A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture

Authors: Masao Taguchi, Hiroyoshi Tomita, Toshiya Uchida, Yasuhiro Ohnishi, Kimiaki Sato, Taiji Ema, Masaaki Higashitani, Takashi Yabu

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique

Authors: Naoto Tomita, Nobuaki Ohtsuka, Jun-ichi Miyamoto, Ken-ichi Imamiya, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Norihisa Arai, Yukio Kaneko, Eiji Sakagami, Kuniyoshi Yoshikawa, Sumio Tanaka

A 64-Mb DRAM with meshed power line

Authors: Toshio Yamada, Yoshiro Nakata, Junko Hasegawa, Noriaki Amano, Akinori Shibayama, Masaru Sasago, Naoto Matsuo, Toshiki Yabu, Susumu Matsumoto, Shozo Okada, Michihiro Inoue

A 15-GHz monolithic two-modulus prescaler

Authors: Yoshiki Yamauchi, Osaake Nakajima, Koichi Nagata, Masahiro Hirayama

Quasi-complementary BiCMOS for sub-3-V digital circuits

Authors: Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi

A 1/3-in 410000-pixel CCD image sensor with feedback field-plate amplifier

Authors: Hajime Akimoto, Haruhisa Ando, Hideki Nakagawa, Yoshihiko Nakahara, Masayuki Hikiba, Hirofumi Ohta

A multirate transceiver IC for four-wire full-duplex data transmission

Authors: Ken Buttle, Hiroshi Takatori, Cheng-Chung Shih, Haim Shafir

DC to 10-GHz mixer and amplifier GaAs ICs for coherent optical heterodyne receiver

Authors: Shuichi Fujita, Yuhki Imai, Yasuro Yamane, Hiroshi Fushimi

A programmable mixed-signal ASIC for power metering

Authors: Steven L. Garverick, Kenji Fujino, Donald T. McGrath, Richard D. Baertsch

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI

Authors: Junichi Goto, Koichi Ando, Toshiaki Inoue, Masakazu Yamashina, Hachiro Yamada, Tadayoshi Enomoto

A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONET STS-192 system

Authors: Kenji Ishida, Hirotsugu Wakimoto, Kunio Yoshihara, Mitsuo Konno, Shoichi Shimizu, Yoshiaki Kitaura, Kenichi Tomita, Takashi Suzuki, Naotaka Uchitomi

A 1/3-in interline transfer CCD image sensor with a negative-feedback-type charge detector

Authors: Yoshiyuki Matsunaga and Shinji Ohsawa

A CCD video delay line with charge-integrating amplifier

Authors: Takashi Miida, Yasumasa Hasegawa, Tatsuya Hagiwara, Hisashi Ohshiba

A 300-MPOS video signal processor with a parallel architecture

Authors: Toshihiro Minami, Ryota Kasai, Hironori Yamauchi, Yutaka Tashiro, Jun-ichi Takahashi, Shigeru Date

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI

Authors: Fuyuki Okamoto, Yasuhiko Hagihara, Chie Ohkubo, Naoki Nishi, Hachiro Yamada, Tadayoshi Enomoto

A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities

Authors: David B. Ribner, Richard D. Baertsch, Steven L. Garverick, Donald T. McGrath, Joseph E. Krisciunas, Toshiaki Fujii

This list is based on the data extracted from dblp: IEEE J. Solid State Circuits

IEEE Networking

Congestion control and prevention in ATM networks

Authors: Duke P. Hong and Tatsuya Suda

This list is based on the data extracted from dblp: IEEE Networking

IEEE Transactions Biomedical Eng.

Deterioration of average evoked potential waveform due to asynchronous averaging and its compensation

Authors: Masatoshi Nakamura, Shigeto Nishida, Hiroshi Shibasaki

Describing head shape with surface harmonic expansions

Authors: Christopher Purcell, Takunori Mashiko, Kazumi Odaka, Keiichi Ueno

Nonlinear interpolation of mandibular kinesiographic signals by applying sensitivity method to a GMDH correction model

Authors: Motoyasu Nagata, Kenji Takada, Mamoru Sakuda

Measurements of dental cast profile and three-dimensional tooth movement during orthodontic treatment

Authors: Katsuyuki Yamamoto, Syunsuke Hayashi, Hirofumi Nishikawa, Shinji Nakamura, Tomohisa Mikami

A blind mobility aid modeled after echolocation of bats

Authors: Tohru Ifukube, Tadayuki Sasaki, Chen Peng

Perceived locus and intensity of electrocutaneous stimulation

Authors: Atsuki Higashiyama and Gary B. Rollman

Control of specific absorption rate distribution using capacitive electrodes and inductive aperture-type applicators: implications for radiofrequency hyperthermia

Authors: Hirokazu Kato, Jeffrey W. Hand, Michael V. Prior, Masahiko Furukawa, Osamu Yamamoto, Tetsuya Ishida

New noninvasive transcutaneous approach to blood glucose monitoring: successful glucose monitoring on human 75 g OGTT with novel sampling chamber

Authors: Shinsuke Kayashima, Tsunenori Arai, Makoto Kikuchi, Noriharu Sato, Naokazu Nagata, Osamu Takatani, Narushi Ito, Jun Kimura, Toshihide Kuriyama, Aiko Kaneyoshi

Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions

Author: Tsutomu Sasao

On the basic principles of radar polarimetry: the target characteristic polarization state theory of Kennaugh, Huynen's polarization fork concept, and its extension to the partially polarized case

Authors: Wolfgang-Martin Boerner, Wei-Ling Yan, An-Qing Xi, Yoshio Yamaguchi

Wave propagation and scattering in random media and rough surfaces

Author: Akira Ishimaru

Amorphous alloy core distribution transformers

Authors: Harry W. Ng, Ryusuke Hasegawa, Albert C. Lee, Larry A. Lowdermilk

This list is based on the data extracted from dblp: Proc. IEEE