IEEE Journals & Magazines 1992 Papers Published by Researchers in Japan in 1992

This webpage may contain errors. Please do NOT trust the following list, although the maintainer has tried his best to correct the mistakes. If you find an error, please contact the maintainer via email at “contact [at] ishikawa.cc”.

Highly contributed researchers in 1992

Shuzo Kato (6)

Katsuro Sasaki (5) / Shuji Kubota (4) / Hideto Hidaka (4) / Kazutami Arimoto (4) / Kazuyasu Fujishima (4) / Koichiro Ishibashi (4)

IEEE Commun. Mag.

User interface design for SONET networks

Authors: Masao Hibino and Frank Kaplan

Implementation in Japan

Author: Osamu Inoue

Evolving from narrowband

Author: Hiroshi Ishikawa

Personalizing ISDN

Author: Tomoyoshi Takebayashi

Global corporate networks in Japan

Authors: Keisuke Tomaru, Toshiki P. Tanaka, Takeki Katsube

Engineering education in Japan

Author: Nobumasa Takahashi

This list is based on the data extracted from dblp: IEEE Commun. Mag.

IEEE J. Sel. Areas Commun.

Signal Processing for Future Home-Use Digital VTR's

Author: Yoshizumi Eto

A 128 kb/s Hi-Fi Audio CODEC Based on Adaptive Transform Coding with Adaptive Block Size MDCT

Authors: Masahiro Iwadare, Akihiko Sugiyama, Fumie Hazu, Akihiro Hirano, Takao Nishitani

A 130 Mb/s Compact HDTV CODEC Based on a Motion-Adaptive DCT Algorithm

Authors: Taizo Kinoshita and Tomoko Nakahashi

Professional HDTV Digital Recorder

Author: Masuo Umemoto

A Global Message Network Employing Low Earth-Orbiting Satellites

Authors: Jaidev Kaniyil, Jun Takei, Shigeru Shimamoto, Yoshikuni Onozato, Tomonori Usui, Ikuo Oka, Tsutomu Kawabata

A TDMA Satellite Communication System for ISDN Services

Authors: Shuzo Kato, Masahiro Morikura, Shuji Kubota, Hiroshi Kazama, Kiyoshi Enomoto, Masahiro Umehira

A New Satellite Communication System Integrated into Public Switched Networks. - DYANET

Authors: Masahumi Ohnuki, Masahiro Umehira, Hiroshi Nakashima, Shuzo Kato

SS/FDMA Router for Flexible Satellite Communications Networks

Authors: Hideyuki Shinonaga and Yasuhiko Ito

Link-Level Connection Control Schemes in a High-Speed Satellite Data Network: A Performance Comparison

Author: Shuji Tasaka

Two-Channel Conjugate Vector Quantizer for Noisy Channel Speech Coding

Author: Takehiro Moriya

Subband Image Coding Using Entropy-Coded Quantization over Noisy Channels

Authors: Naoto Tanabe and Nariman Farvardin

Transmission of SDH Signals Through Future Satellite Channels Using High-Level Modulation Techniques

Authors: Hamid Aghvami, Orhan Gemikonakli, Shuzo Kato

Novel Satellite Digital Video TDMA System for Business Video Communications

Authors: Shuzo Kato, Shuji Kubota, Hiroshi Kazama, Masahiro Morikura

DSD (Double Soft Decision) Concatenated FEC Scheme in Mobile Satellite Communication Systems

Authors: Shunji Honda, Shuji Kubota, Shuzo Kato

A New Carrier Recovery Circuit for Land Mobile Satellite Communication

Authors: Kiyoshi Kobayashi, Tsotumo Sakai, Shuji Kubota, Masahiro Morikura, Shuzo Kato

Introduction Strategy and Technologies for ATM VP-Based Broadband Networks

Authors: Tomonori Aoyama, Ikuo Tokizawa, Ken-ichi Sato

B-ISDN Multimedia Communication and Collaboration Platform Using Advanced Video Workstations to Support Cooperative Work

Authors: Tohru Hoshi, Kenjiro Mori, Yasuhiro Takahashi, Yoshiyuki Nakayama, Takeshi Ishizaki

Granulated Broadband Network Applicable to B-ISDN and PSTN Services

Authors: Yuji Inoue, Noriyuki Terada, Masatoshi Kawarasaki, Ko-ichi Sano, Koji Ikuta

Deployment of ATM Subscriber Line Systems

Authors: Toshinori Tsuboi, Youichi Maeda, Kazuhiro Hayashi, Katsuaki Kikuchi

This list is based on the data extracted from dblp: IEEE J. Sel. Areas Commun.

IEEE J. Solid State Circuits

High-frequency operation of quantum flux parametron (QFP) based shift registers and frequency prescalers

Authors: Juan Casas, Ryotaro Kamikawai, Eiichi Goto

An experimental single-chip data flow CPU

Authors: Gregory A. Uvieghara, Wen-mei W. Hwu, Yoshinobu Nakagome, Deog-Kyoon Jeong, David D. Lee, David A. Hodges, Yale N. Patt

A high-speed halftoning processor for raster scanned images

Authors: Toshiharu Kurosawa and Yuji Maruyama

A 1.5-ns access time, 78- mu m2 memory-cell size, 64-kb ECL-CMOS SRAM

Authors: Kunihiko Yamaguchi, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Toshiro Hiramoto, Nobuo Tamba, Kunihiko Watanabe, Masanori Odaka, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai

A CMOS four-channel*1K time memory LSI with 1-ns/b resolution

Authors: Yasuo Arai, Tsuneo Matsumura, Ken-ichi Endo

An 80-MFLOPS (peak) 64-b microprocessor for parallel computer

Authors: Hiraku Nakano, Masaitsu Nakajima, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

Authors: Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki

Cell-plate line connecting complementary bit-line (C3) architecture for battery-operated DRAMs

Authors: Mikio Asakura, Kazutami Arimoto, Hideto Hidaka, Kazuyasu Fujishima

A dual-mode sensing scheme of capacitor-coupled EEPROM cell

Authors: Masanori Hayashikoshi, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima

A high-density dual-port memory cell operation and array architecture for ULSI DRAMs

Authors: Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima

A 1.7-V adjustable I/O interface for low-voltage fast SRAMs

Authors: Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima

High-speed CMOS I/O buffer circuits

Authors: Manabu Ishibe, Shoji Otaka, Junichi Takeda, Shigeru Tanaka, Yoshiaki Toyoshima, Satoru Takatsuka, Shoichi Shimizu

A design technique for a high-gain, 10-GHz class-bandwidth GaAs MESFET amplifier IC module

Authors: Noboru Ishihara, Eiichi Sano, Yuhki Imai, Hiroyuki Kikuchi, Yasuro Yamane

Highly parallel collision detection processor for intelligent robots

Authors: Michitaka Kameyama, Tadao Amada, Tatsuo Higuchi

Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs

Authors: Hideo Kato, Katsuhiko Sato, Masataka Matsui, H. Shibata, K. Hashimoto, Takayuki Ootani, Kiyofumi Ochii

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAMs

Authors: Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh

Automated bias control (ABC) circuit for high-performance VLSIs

Authors: Tadahiro Kuroda, Toshiyuki Fukunaga, Kenji Matsuo, Kazuhiko Kasai, Ayako Hirata, Shinji Fujii, Masahiro Kimura, Hiroaki Suzuki

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Authors: Yoshikazu Miyawaki, Takeshi Nakayama, Shin'ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

Limitations, innovations, and challenges of circuits and devices into a half micrometer and beyond

Author: Minoru Nagata

An enhanced fully differential folded-cascode op amp

Authors: Katsufumi Nakamura and L. Richard Carley

High-speed sensing techniques for ultrahigh-speed SRAMs

Authors: Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Kunihiko Yamaguchi, Toshiro Hiramoto, Nobuo Tamba, Masanori Odaka, Kunihiko Watanabe, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai

A 250-Mb/s, 700-mW, 32-highway*8-b S/P converter LSI with cross-access memory

Authors: Yusuke Ohtomo and Masao Suzuki

A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Authors: Masahiro Ohuchi, Toshihiko Okamura, Akihiro Sawairi, F. Kuniba, K. Matsumoto, Tsutomu Tashiro, S. Hatakeyama, K. Okuyama

Fault-tolerant architecture in a cache memory control LSI

Authors: Yasushi Ooi, Masahiko Kashimura, Hidenori Takeuchi, Eiji Kawamura

An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit

Authors: Tomio Sato, Masato Sakate, H. Okada, T. Sukemura, Gensuke Goto

A pulsed sensing scheme with a limited bit-line swing

Authors: Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong

Word-line architecture for highly reliable 64-Mb DRAM

Authors: Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi

A 100-MHz 2-D discrete cosine transform core processor

Authors: Shin-ichi Uramoto, Yoshitsugu Inoue, Akihiko Takabatake, Jun Takeda, Yukihiro Yamashita, Hideyuki Terane, Masahiko Yoshimoto

A 1-V operating 256-kb full-CMOS SRAM

Authors: Akinori Sekiyama, Teruo Seki, Shinji Nagai, Akihiro Iwase, Noriyuki Suzuki, Masato Hayasaka

A voltage down converter with submicroampere standby current for low-power static RAMs

Authors: Koichiro Ishibashi, Katsuro Sasaki, Hiroshi Toyoshima

A 2 K-word dictionary search processor (DISP) LSI with an approximate word search capability

Authors: Masato Motomura, Hachiro Yamada, Tadayoshi Enomoto

A MOSFET-C variable equalizer circuit with simple on-chip automatic tuning

Authors: Satoshi Sakurai, Mohamnmed Ismail, Jean-Yves Michel, Edgar Snchez-Sinencio, Robert Brannen

A floating-point cell library and a 100-Mflops image signal processor

Authors: Hiroshige Fujii, Chikahiro Hori, Tomoji Takada, Naoyuki Hatanaka, Tatsuhiko Demura, Goichi Ootomo

A 34-ns 16-Mb DRAM with controllable voltage down-converter

Authors: Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima

A unified theory for mixed CMOS/BiCMOS buffer optimization

Author: Takayasu Sakurai

Design and implementation of a 3D-LSI image sensing processor

Authors: Kazumasa Kioi, Toshiyuki Shinozaki, Shinji Toyoyama, Kazuhiko Shirakawa, Koui Ohtake, Shuhei Tsuchimoto

An analytical access time model for on-chip cache memories

Authors: Tomohisa Wada, Suresh Rajan, Steven A. Przybylski

A 54*54-b regularly structured tree multiplier

Authors: Gensuke Goto, Tomio Sato, Masao Nakajima, Takao Sukemura

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

Authors: Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa

An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Si bipolar technology

Authors: Katsuyoshi Washio, Takeaki Okabe, Katsuhiro Norisue, Toshio Nagashima

A limiting amplifier with low phase deviation using an AlGaAs/GaAs HBT

Authors: Makoto Nakamura, Yuhki Imai, Eiichi Sano, Yoshiki Yamauchi, Osaake Nakajima

MMIC family for DBS down-converter with pulse-doped GaAs MESFETs

Authors: Nobuo Shiga, Takeshi Sekiguchi, Shigeru Nakajima, Kenji Otobe, Nobuhiro Kuwata, Ken-ichiro Matsuzaki, Hideki Hayashi

Pseudomorphic 2DEG FET ICs for 10 Gb/s optical communication systems with external optical modulation

Authors: Yasuyuki Suzuki, Tetsuyuki Suzaki, Yumi Ogawa, Sadao Fujita, Wendy Liu, Akihiko Okamoto

Monolithic integration of 5-Gb/s optical receiver block for short distance communication

Authors: Chiaki Takano, Kiyoshi Tanaka, Akihiko Okubora, Jiro Kasahara

Logic circuits using resonant-tunneling hot-electron transistors (RHETs)

Authors: Motomu Takatsu, Kenichi Imamura, Hiroaki Ohnishi, Toshihiko Mori, Takami Adachihara, Shunichi Muto, Naoki Yokoyama

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer ICs using GaAs DCFL circuit

Authors: Koutarou Tanaka, Makoto Shikata, Tamotsu Kimura, Yoshiaki Sano, Masahiro Akiyama

A 15-GHz monolithic low-phase-noise VCO using AlGaAs/GaAs HBT technology

Authors: Yoshiki Yamauchi, Hideki Kamitsuna, Masashi Nakatsugawa, Hiroshi Ito, Masahiro Muraguchi, Kazuo Osafune

A low-current Ku-band GaAs monolithic image rejection down-converter

Authors: Toshihiko Yoshimasu, Keiichi Sakuno, Nobuyuki Matsumoto, Eiji Suematsu, Toshiya Tsukao, Takashi Tomita

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

Authors: Katsumi Dosaka, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara

A 3.3-V 12-ns 16-Mb CMOS SRAM

Authors: Hiroyuki Goto, Hiroaki Ohkubo, Kenji Kondou, Masayoshi Ohkawa, Hitoshi Mitani, Shinichi Horiba, Masakazu Soeda, Fumihiko Hayashi, Yutaro Hachiya, Toshiyuki Shimizu, Manabu Ando, Zensuke Matsuda

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file

Authors: Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba

A 1.5-V full-swing BiCMOS logic circuit

Authors: Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki

A 1-V TFT-load SRAM using a two-step word-voltage method

Authors: Koichiro Ishibashi, Koichi Takasugi, Toshiaki Yamanaka, Takashi Hashimoto, Katsuro Sasaki

A 5-V-only 16-Mb flash memory with sector erase mode

Authors: Toshikatsu Jinbo, Hidetoshi Nakata, Kiyokazu Hashimoto, Takeshi Watanabe, Kazuhisa Ninomiya, Takahiko Urai, Mikio Koike, Tatsuo Sato, Noriaki Kodama, Ken-ichi Oyama, Takeshi Okazawa

A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture

Authors: Masato Matsumiya, Shoichiro Kawashima, Makoto Sakata, Masahiko Ookura, Toru Miyabo, Tom Koga, Kazuo Itabashi, Kazuhiro Mizutani, Hiroshi Shimada, Noriyuki Suzuki

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

Authors: Kazuyuki Nakamura, Takashi Oguri, Takao Atsumo, Masahide Takada, Atsushi Ikemoto, Hisamitsu Suzuki, Tadashi Nishigori, Tohru Yamazaki

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

Authors: Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu

A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array

Authors: Katsuyuki Sato, Mitsuteru Kobayashi, Hiroyuki Hida, Hideyuki Miyazawa, Yuji Shirai, Kenji Fujita, Toshiyuki Nakao, Masamichi Ishihara

A 9.5-Gb/s Si-bipolar ECL array

Authors: Masaya Tamamura, Shinichi Shiotsu, Masayasu Hojo, Katsunobu Nomura, Shinji Emori, Hiromichi Ichikawa, Takao Akai

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

Authors: Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

Authors: Akira Umezawa, Shigeru Atsumi, Masao Kuriyama, Hironori Banba, Ken-ichi Imamiya, Kiyomi Naruke, Seiji Yamada, Etsushi Obi, Masamitsu Oshikiri, Tomoko Suzuki, Sumio Tanaka

A video digital signal processor with a vector-pipeline architecture

Authors: Kunitoshi Aono, Masaki Toyokura, Toshiyuki Araki, Akihiko Ohtani, Hisashi Kodama, Kiyoshi Okamoto

A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses

Authors: Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara

A Si bipolar 28-GHz dynamic frequency divider

Authors: Masakazu Kurisu, Gohiko Uemura, Masahiro Ohuchi, Chihiro Ogawa, Hisashi Takemura, Takenori Morikawa, Tsutomu Tashiro

A 3-mW 1.0-GHz silicon-ECL dual-modulus prescaler IC

Authors: Moriaki Mizuno, Hirokazu Suzuki, Masami Ogawa, Kouji Sato, Hiromichi Ichikawa

10-GHz Si bipolar amplifier and mixer ICs for coherent optical systems

Authors: Toshiyuki Okamura, Chiharu Kurioka, Yoshiaki Kuraishi, Orie Tsuzuki, Takashi Senba, Mizuyuki Ushirozawa, Mikio Fujimaru

Neuro chips with on-chip back-propagation and/or Hebbian learning

Authors: Takeshi Shima, Tomohisa Kimura, Yukio Kamatani, Tetsuro Itakura, Yasuhiko Fujita, Tetsuya Iida

Si bipolar chip set for 10-Gb/s optical receiver

Authors: Tetsuyuki Suzaki, Masaaki Soda, Takenori Morikawa, Hiroshi Tezuka, Chihiro Ogawa, Sadao Fujita, Hisashi Takemura, Tsutomu Tashiro

A high-speed digital neural network chip with low-power chain-reaction architecture

Authors: Kuniharu Uchimura, Osamu Saito, Yoshihito Amemiya

A 1.2- mu m BiCMOS sample-and-hold circuit with a constant-impedance, slew-enhanced sampling gate

Authors: Myles H. Wakayama, Hiroshi Tanimoto, Takahiro Tasai, Yoshihiro Yoshida

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure

Authors: Tadato Yamagata, Masaaki Mihara, Takeshi Hamamoto, Yasumitsu Murai, Toshifumi Kobayashi, Michihiro Yamada, Hideyuki Ozaki

This list is based on the data extracted from dblp: IEEE J. Solid State Circuits

IEEE Trans. Biomed. Eng.

Development of a new geometrical form of micropipette: electrical characteristics and an application as a potassium ion selective electrode

Authors: Paulo Jos Abatti and Toyosaka Moriizumi

448-Detector optical recording system: development and application to Aplysia gill-withdrawal reflex

Authors: Michio Nakashima, Satoshi Yamada, Satoru Shiono, Mitsuo Maeda, Fumihide Satoh

A muscle fatigue index based on the relationship between preceding background activity, and myotatic reflex response (MRR)

Authors: Tohru Kiryu, Yoshiaki Saitoh, Kiyoshi Ishioka

Investigation on parametric analysis of dynamic EMG signals by a muscle-structured simulation model

Authors: Tohru Kiryu, Yoshiaki Saitoh, Kiyoshi Ishioka

An automatic control algorithm for the optimal driving of the ventricular-assist device

Authors: Makoto Yoshizawa, Hiroshi Takeda, Takeshi Watanabe, Makoto Miura, Tomoyuki Yambe, Yoshiaki Katahira, Shin-ichi Nitta

A multimicroelectrode system composed of independent glass micropipettes with an eccentric tip structure for simultaneous intracellular recording

Authors: Masahisa Saburi, Masahiro Yamada, Yukifumi Shigematsu

Maximum-likelihood estimation of current-dipole parameters for data obtained using multichannel magnetometer

Authors: Kensuke Sekihara, Yukiko Ogura, Masao Hotta

Clinical application of an active electrode using an operational amplifier

Authors: Suzushi Nishimura, Yutaka Tomita, Toshio Horiuchi

Ambulatory oxygen uptake measurement system

Authors: Toshiyo Tamura, Kazuhiko Sato, Tatsuo Togawa

This list is based on the data extracted from dblp: IEEE Trans. Biomed. Eng.

IEEE Trans. Circuits Syst. Video Technol.

An all-ASIC implementation of a low bit-rate video codec

Authors: Hiroshi Fujiwara, Ming L. Liou, Ming-Ting Sun, Kun-Min Yang, Masanori Maruyama, Kazuyoshi Shomura, Koichi Ohyama

Chrominance/luminance signal separation and syntheses chips developed with a DSP silicon compiler

Authors: Takashi Miyazaki, Takao Nishitani, Masaki Ishikawa, Masato Edahiro, Kaoru Mitsuhashi

Architecture and implementation of a highly parallel single-chip video DSP

Authors: Hironori Yamauchi, Yutaka Tashiro, Toshihiro Minami, Yutaka Suzuki

Design and implementation of multidimensional Y-C separation filters for NTSC signals

Authors: Toshiyuki Yoshida, Katsumi Ashizawa, Akinori Nishihara

This list is based on the data extracted from dblp: IEEE Trans. Circuits Syst. Video Technol.

IEEE Trans. Commun.

Time compression multiplex transmission system using a 1.3 μm semiconductor laser as a transmitter and a receiver

Author: Norio Kashima

Analysis of a new thruway communication system with discrete minimal zones

Authors: Paulo B. Ges, Hironao Kawashima, Ushio Sumita

Dynamic bandwidth control of the virtual path in an asynchronous transfer mode network

Authors: Satoru Ohta and Ken-ichi Sato

Performance analysis of nonblocking packet switch with input and output buffers

Authors: Yuji Oie, Masayuki Murata, Koji Kubota, Hideo Miyahara

Call admission control in an ATM network using upper bound of cell loss probability

Author: Hiroshi Saito

A model for evaluating talker echo and sidetone in a telephone transmission network

Authors: Naotoshi Osaka, Kazuhiko Kakehi, Satori Iai, Nobuhiko Kitawaki

This list is based on the data extracted from dblp: IEEE Trans. Commun.

IEEE Trans. Computers

P-Functions-Ternary Logic Functions Capable of Correcting Input Failures and Suitable for Treating Ambiguities

Authors: Yoshinori Yamamoto and Masao Mukaidono

A Testable Design of Logic Circuits under Highly Observable Condition

Authors: Xiaoqing Wen and Kozo Kinoshita

Cache Memories for Data Flow Machines

Author: Masaru Takesue

Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem

Authors: Naofumi Takagi and Shuzo Yajima

A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation

Author: Naofumi Takagi

Task Allocation for Maximizing Reliability of Distributed Computer Systems

Authors: Sol M. Shatz, Jia-Ping Wang, Masanori Goto

This list is based on the data extracted from dblp: IEEE Trans. Computers

IEEE Trans. Image Process.

Backprojection by upsampled Fourier series expansion and interpolated FFT

Authors: Makoto Tabei and Mitsuhiro Ueda

Vector quantization for entropy coding of image subbands

Authors: Takanori Senoo and Bernd Girod

This list is based on the data extracted from dblp: IEEE Trans. Image Process.

IEEE Trans. Inf. Theory

Improved variations relating the Ziv-Lempel and Welch-type algorithms for sequential data compression

Author: Hidetoshi Yokoo

Identifiability of hidden Markov information sources and their minimum degrees of freedom

Authors: Hisashi Ito, Shun-ichi Amari, Kingo Kobayashi

Correction to 'Source coding for average rate and average distortion: A new variable-length coding theorems' (Nov 83 785-792)

Author: Takeshi Hashimoto

IEEE Trans. Parallel Distributed Syst.

Coterie Join Algorithm

Authors: Mitchell L. Neilsen and Masaaki Mizuno

Checkpointing for Distributed Databases: Starting from the Basics

Authors: Slawomir Pilarski and Tiko Kameda

This list is based on the data extracted from dblp: IEEE Trans. Parallel Distributed Syst.

IEEE Journals & Magazines 1992

Papers Published by Researchers in Japan in 1992