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A Vision System With 1-inch 17-Mpixel 1000-fps Block-Controlled Coded-Exposure Stacked-CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range Control
Authors: Tomoki Hirata, Hironobu Murata, Taku Arii, Hideaki Matsuda, Hajime Yonemochi, Yojiro Tezuka, Shiro Tsunai
A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network
Authors: Atsutake Kosuge, Yao-Chung Hsu, Mototsugu Hamada, Tadahiro Kuroda
A Nearly Interference-Free and Depth-Resolution-Configurable Time-of-Flight System Based on a Mega-Pixel Vertical Avalanche Photodiodes CMOS Image Sensor
Authors: Shota Yamada, Motonori Ishii, Shigetaka Kasuga, Masato Takemoto, Hiromu Kitajima, Toru Okino, Yusuke Sakata, Manabu Usuda, Yugo Nose, Hiroshi Koshida, Masaki Tamaru, Akito Inoue, Yuki Sugiura, Shigeru Saito, Taiki Kunikyo, Yusuke Yuasa, Kentaro Nakanishi, Naoki Torazawa, Takashi Shirono, Tatsuya Kabe, Shinzo Koyama, Mitsuyoshi Mori, Yutaka Hirose, Masayuki Sawada, Akihiro Odagawa, Tsuyoshi Tanaka
Energy Efficiency of Uplink Cell-Free Massive MIMO With Transmit Power Control in Measured Propagation Channel
Authors: Thomas Choi, Masaaki Ito, Issei Kanno, Jorge Gomez-Ponce, Colton Bullard, Takeo Ohseki, Kosuke Yamazaki, Andreas F. Molisch
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices
Authors: Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching
Authors: Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches
Authors: Hayato Yoshida, Yusaku Shiotsu, Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS
Authors: Atsuki Kobayashi and Kiichi Niitsu