Highly contributed researchers
In recent 10 years: Takahiro Hanyu (5)
Naoya Onizawa (4) / Yoshifumi Nishio (2) / Hiroo Sekiya (2) / Yoko Uwate (2) / Hideo Ohno (2) / Takuya Sakamoto (2)
Since 2011: Takahiro Hanyu (5)
Naoya Onizawa (4)
Statistics
Investigating Packet Transmission From the Perspective of Complex Networks Composed of Chaotic Circuits
Authors: Souhei Shima, Tsuyoshi Isozaki, Yoko Uwate, Yoshifumi Nishio
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing
Authors: Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
CellularFlow: Memristive Circuits of Gyrator Neurons Toward Brain Circuits
Authors: Mamoru Tanaka, Yoshifumi Nishio, Hiroo Sekiya, Masaki Bandai, Yuichi Tanji, Yoko Uwate
Graph Kernels Encoding Features of All Subgraphs by Quantum Superposition
Authors: Kaito Kishi, Takahiko Satoh, Rudy Raymond, Naoki Yamamoto, Yasubumi Sakakibara
Design of Efficient AI Accelerator Building Blocks in Quantum-Dot Cellular Automata (QCA)
Authors: Ahmed Mamdouh, Mbonea Mjema, Grta Yemisioglu, Satoshi Kondo, Ali Muhtaroglu
Testing Scalable Bell Inequalities for Quantum Graph States on IBM Quantum Devices
Authors: Bo Yang, Rudy Raymond, Hiroshi Imai, Hyungseok Chang, Hidefumi Hiraishi
A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net
Authors: Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
Transfer Learning for Semi-Supervised Automatic Modulation Classification in ZF-MIMO Systems
Authors: Yu Wang, Guan Gui, Haris Gacanin, Tomoaki Ohtsuki, Hikmet Sari, Fumiyuki Adachi
Dropout and DropConnect for Reliable Neuromorphic Inference Under Communication Constraints in Network Connectivity
Authors: Yasufumi Sakai, Bruno U. Pedroni, Siddharth Joshi, Satoshi Tanabe, Abraham Akinin, Gert Cauwenberghs
Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration
Authors: Massimo Giordano, Giorgio Cristiano, Koji Ishibashi, Stefano Ambrogio, Hsinyu Tsai, Geoffrey W. Burr, Pritish Narayanan
Emerging MPEG Standards for Point Cloud Compression
Authors: Sebastian Schwarz, Marius Preda, Vittorio Baroncini, Madhukar Budagavi, Pablo Csar, Philip A. Chou, Robert A. Cohen, Maja Krivokuca, Sebastien Lasserre, Zhu Li, Joan Llach, Khaled Mammou, Rufael Mekuria, Ohji Nakagami, Ernestasia Siahaan, Ali J. Tabatabai, Alexis M. Tourapis, Vladyslav Zakharchenko
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling
Authors: Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
Motion Compensation for an Unmanned Aerial Vehicle Remote Radar Life Sensor
Authors: Robert H. Nakata, Brian Haruna, Takashi Yamaguchi, Victor M. Lubecke, Shigeru Takayama, Kiyotsugu Takaba
Doppler Radar Techniques for Accurate Respiration Characterization and Subject Identification
Authors: Ashikur Rahman, Victor M. Lubecke, Olga Boric-Lubecke, Jan H. Prins, Takuya Sakamoto
Noncontact Measurement of the Instantaneous Heart Rate in a Multi-Person Scenario Using X-Band Array Radar and Adaptive Array Processing
Authors: Takuya Sakamoto, Pascal Aubry, Shigeaki Okumura, Hirofumi Taki, Toru Sato, Alexander G. Yarovoy
Low Latency IDMA With Interleaved Domain Architecture for 5G Communications
Authors: Tran Thi Thao Nguyen, Leonardo Lanante, Shingo Yoshizawa, Hiroshi Ochi
Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors
Authors: Islam A. K. M. Mahfuzul, Masamune Hamamatsu, Tomoyuki Yokota, Sunghoon Lee, Wakako Yukita, Makoto Takamiya, Takao Someya, Takayasu Sakurai
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
Authors: Toshiaki Kirihata, John Golz, Matthew R. Wordeman, Pooja Batra, Gary W. Maier, Norman Robson, Troy L. Graves-abe, Daniel Berger, Subramanian S. Iyer
Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM
Authors: Takao Nomura, Ryo Mori, Koji Takayanagi, Kazuki Fukuoka, Koji Nii
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories
Authors: Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno
Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications
Authors: Vincent C. Gaudet, Jon T. Butler, Robert Wille, Naofumi Homma
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification
Authors: Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks
Authors: Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross
Multiple-Valued Signaling for High-Speed Serial Links Using Tomlinson-Harashima Precoding
Authors: Yasushi Yuminaka and Yosuke Iijima
Stability Analysis of Multi-Phase Synchronization in Paralleled Buck Converters With Winner-Take-All and Loser-Take-All Switching Rules
Authors: Toshiyasu Ohata and Toshimichi Saito
Design of a DC-DC Converter With Phase-Controlled Class-D ZVS Inverter
Authors: Yuta Yamada, Tomoharu Nagashima, Yoshifumi Ibuki, Yoshiki Fukumoto, Tatsuya Ikenari, Hiroo Sekiya
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture
Authors: Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
Design of Simultaneous Bi-Directional Transceivers Utilizing Capacitive Coupling for 3DICs in Face-to-Face Configuration
Authors: Myat Thu Linn Aung, Eric Teck Heng Lim, Takefumi Yoshikawa, Tony Tae-Hyoung Kim
A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM
Authors: Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda
Power-Efficient Hardware Architecture of K-Means Clustering With Bayesian-Information-Criterion Processor for Multimedia Processing Applications
Authors: Tse-Wei Chen, Chih-Hao Sun, Hsiao-Hang Su, Shao-Yi Chien, Daisuke Deguchi, Ichiro Ide, Hiroshi Murase