IEEE Journal of Solid-State Circuits

In recent 10 years: Kenichi Okada (29)

Atsushi Shirane (17) / Akira Matsuzawa (12) / Satoshi Kondo (9) / Masaya Miyahara (9) / Ken Takeuchi (9)

Since 1988: Tadahiro Kuroda (45)

Takayasu Sakurai (44) / Kenichi Okada (39) / Ken Takeuchi (30) / Kazutami Arimoto (25)

A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal

Authors: Jongsoo Lee, Jaehyuk Jang, Wooseok Lee, Bosung Suh, Heeyong Yoo, Beomyu Park, Jeongkyun Woo, Inhyo Ryu, Honggul Han, Jaeyoung Kim, Hojung Kang, John H. Kang, Minseob Lee, Danbi Lee, Hyeonuk Son, Suhyeon Lee, Soyeon Kim, Dong-Chan Kim, Dae-Young Yoon, Hongjong Park, Sangsung Lee, Jeongyeol Bae, Huijung Kim, Joonhee Lee, Sangmin Yoo

A -90-dBFS-IM3, -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors

Authors: Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Prawal Shrestha, Zhao Li, Sevil Zeynep Lulec, Konstantinos Vasilakopoulos, Raviteja Theertham, Donald Paterson, Qingnan Yu, Aseer Chowdhury

Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC)

Authors: Ken Takeuchi, Tetsuya Iizuka, Kazuko Nishimura, Jerald Yoo

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering

Authors: Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka

Design of Dual Lower Bound Hysteresis Control in Switched-Capacitor DC-DC Converter for Optimum Efficiency and Transient Speed in Wide Loading Range for IoT Application

Authors: Yi Tan, Cheng Huang, Hiroki Ishikuro

Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium

Author: Kenichi Okada

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

Authors: Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits

Authors: Mototsugu Hamada and Ron Kapusta

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET

Authors: Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS

Authors: Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C

Authors: Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono

A 3.36-μm-Pitch SPAD Photon-Counting Image Sensor Using a Clustered Multi-Cycle Clocked Recharging Technique With an Intermediate Most-Significant-Bit Readout

Authors: Takafumi Takatsuka, Jun Ogi, Yasuji Ikeda, Kazuki Hizu, Yutaka Inaoka, Shunsuke Sakama, Iori Watanabe, Tatsuya Ishikawa, Shohei Shimada, Junki Suzuki, Hidenori Maeda, Kenji Toshima, Yusuke Nonaka, Akifumi Yamamura, Hideki Ozawa, Fumihiko Koga, Yusuke Oike

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration

Authors: Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression

Authors: Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Jill C. Mayeda, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang, Jian Pang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter

Authors: Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada

A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration

Authors: Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro

A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation

Authors: Xi Fu, Dongwon You, Yun Wang, Xiaolin Wang, Ashbir Aviat Fadila, Chenxin Liu, Sena Kato, Chun Wang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada

A 134132 4-Tap CMOS Indirect Time-of-Flight Range Imager Using In-Pixel Memory Array With 10 Kfps High-Speed Mode and High Precision Mode

Authors: Chia-Chi Kuo and Rihito Kuroda

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)

Authors: Mike Shuo-Wei Chen, Visvesh S. Sathe, Massimo Alioto, Jae-Sun Seo, Hidehiro Shiga

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Authors: Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini

MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing

Authors: Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo

A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking

Authors: Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury

A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations

Authors: Xi Fu, Dongwon You, Xiaolin Wang, Yun Wang, Carolyn Jill Mayeda, Yuan Gao, Michihiro Ide, Yuncheng Zhang, Jun Sakamaki, Ashbir Aviat Fadila, Zheng Li, Jumpei Sudo, Makoto Higaki, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai, Kenichi Okada, Atsushi Shirane

A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting

Authors: Manxin Li, Calvin Yoji Lee, Praveen Kumar Venkatachala, Ahmed ElShater, Yuichi Miyahara, Kazuki Sobue, Koji Tomioka, Un-Ku Moon

A Three-Wafer-Stacked Hybrid 15-MPixel CIS + 1-MPixel EVS With 4.6-GEvent/s Readout, In-Pixel TDC, and On-Chip ISP and ESP Function

Authors: Menghan Guo, Shoushun Chen, Zhe Gao, Wenlei Yang, Peter Bartkovjak, Qing Qin, Xiaoqin Hu, Dahai Zhou, Qiping Huang, Masayuki Uchiyama, Yoshiharu Kudo, Shimpei Fukuoka, Chengcheng Xu, Hiroaki Ebihara, Xueqing Wang, Peiwen Jiang, Bo Jiang, Bo Mu, Huan Chen, Jason Yang, TJ Dai, Andreas Suess

Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC)

Authors: SeongHwan Cho, Joo-Young Kim, Minoru Fujishima, Jun Zhou

A 37-43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD

Authors: Yudai Yamazaki, Jun Sakamaki, Jian Pang, Joshua Alvin, Zheng Li, Dongwon You, Jill C. Mayeda, Atsushi Shirane, Kenichi Okada

Guest Editorial IEEE 2022 European Solid-State Circuits Conference

Authors: Makoto Nagata and Massimo Alioto

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

Authors: Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

Authors: Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi

A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks

Authors: Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Timothy F. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, Brent R. Carlton

A Hybrid ToF Image Sensor for Long-Range 3D Depth Measurement Under High Ambient Light Conditions

Authors: Kunihiro Hatakeyama, Yu Okubo, Tomohiro Nakagome, Masahiro Makino, Hiroshi Takashima, Takahiro Akutsu, Takehide Sawamoto, Masanori Nagase, Tatsuo Noguchi, Shoji Kawahito

A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station

Authors: Zheng Li, Jian Pang, Yi Zhang, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Yun Wang, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Jeehoon Park, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada

Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits

Authors: Borivoje Nikolic and Mototsugu Hamada

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS

Authors: Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs

Authors: Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka

A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs

Authors: Thierry Tambe, En-Yu Yang, Glenn G. Ko, Yuji Chai, Coleman Hooper, Marco Donato, Paul N. Whatmough, Alexander M. Rush, David Brooks, Gu-Yeon Wei

DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC

Authors: Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, Hoi-Jun Yoo

A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface

Authors: Jonghak Yuh, Yen-Lung Jason Li, Heguang Li, Yoshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Gwang Yeong Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, Taekeun Han, Masatoshi Okumura, Jiwen Liu, Jeongduk John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Akihiro Matsuda, Chen Chen, Indra K. V, V. S. N. K. Chaitanya G., Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, Farookh Moogat, In-Soo Yoon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Kosuke Yanagidaira, Takuyo Kodama, Ryo Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe

An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer

Authors: Ippei Akita, Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu, Masakazu Hioki

A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas

Authors: Bodhisatwa Sadhu, Arun Paidimarri, Duixian Liu, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Wooram Lee, Kevin Xiaoxiong Gu, Jean-Olivier Plouchart, Christian W. Baks, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia

A Versatile ±25-A Shunt-Based Current Sensor With ±0.25% Gain Error From -40 °C to 85 °C

Authors: Zhong Tang, Roger Luis Brito Zamparette, Yoshikazu Furuta, Tomohiro Nezuka, Kofi A. A. Makinwa

Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)

Authors: Wanghua Wu, Hiroyuki Ito, Jens Anders, Ahmed M. A. Ali, Gal Pillonnet

A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR

Authors: Yi Zhang, Jian Pang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology

Authors: Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman

A 76-Gbit/s 265-GHz CMOS Receiver With WR-3.4 Waveguide Interface

Authors: Shinsuke Hara, Ruibing Dong, Sangyeop Lee, Kyoya Takano, Naoya Toshida, Akifumi Kasamatsu, Kunio Sakakibara, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima

A 30.2- Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera

Authors: Fukashi Morishita, Wataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Masao Ito

A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier

Authors: Masaya Nakano, Yoshinobu Kaneda, Satoru Nakanishi, Yasumitsu Murai, Yosuke Tashiro, Yasuhiko Taito, Tomoya Ogawa, Hidenori Mitani, Takashi Ito, Takashi Kono

A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation

Authors: Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada

A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC

Authors: Hao Qiu, Takayasu Sakurai, Makoto Takamiya

A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement

Authors: Ruilin Zhang, Xingyu Wang, Kunyang Liu, Hirofumi Shinohara

Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation

Authors: Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada

An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BLE Frequency Modulation

Authors: Yuming He, Johan H. C. van den Heuvel, Paul Mateman, Erwin Allebes, Stefano Traferro, Johan Dijkhuis, Keigo Bunsen, Peter Vis, Arjan Breeschoten, Yao-Hong Liu, Tomohiro Matsumoto, Christian Bachmann

Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL

Authors: Zhaowen Wang, Yudong Zhang, Yuka Onizuka, Peter R. Kinget

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

Authors: Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi, Ryuichi Fujimoto

A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer

Authors: Michihiro Ide, Atsushi Shirane, Kiyoshi Yanagisawa, Dongwon You, Jian Pang, Kenichi Okada

Guest Editorial Introduction to the Special Issue on the 2021 Symposium on VLSI Circuits

Authors: Yusuke Oike and Borivoje Nikolic

Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front End

Authors: Ji-Seon Paek, Dong-Su Kim, Jae-Yeol Han, Young-Hwan Choo, Jun-Suk Bang, Seungchan Park, Jongbeom Baek, Takahiro Nomiyama, Ik-Hwan Kim, Jongwoo Lee

A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC

Authors: Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda

A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal

Authors: Yun Wang, Dongwon You, Xi Fu, Takeshi Nakamura, Ashbir Aviat Fadila, Teruki Someya, Atsuhiro Kawaguchi, Junjun Qiu, Jian Pang, Kiyoshi Yanagisawa, Bangan Liu, Yuncheng Zhang, Haosheng Zhang, Rui Wu, Shunichiro Masaki, Daisuke Yamazaki, Atsushi Shirane, Kenichi Okada

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)

Authors: Amir Amirkhany, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control

Authors: Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei

An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With -93-dB THD+N, 113-dB SNR, and 93% Efficiency

Authors: Atsushi Matamura, Naoaki Nishimura, Preston Birdsong, Abhishek Bandyopadhyay, Adam Spirer, Mariana T. Markova, Shaolong Liu

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Authors: Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Jian Pang, Hanli Liu, Masaya Miyahara, Atsushi Shirane, Kenichi Okada

A Fill-In Technique for Robust IMD Suppression in Chopper Amplifiers

Authors: Thije Rooijers, Shoubhik Karmakar, Yoshinori Kusuda, Johan H. Huijsing, Kofi A. A. Makinwa

A 124-dB Dynamic-Range SPAD Photon-Counting Image Sensor Using Subframe Sampling and Extrapolating Photon Count

Authors: Jun Ogi, Takafumi Takatsuka, Kazuki Hizu, Yutaka Inaoka, Hongbo Zhu, Yasuhisa Tochigi, Yoshiaki Tashiro, Fumiaki Sano, Yusuke Murakawa, Makoto Nakamura, Yusuke Oike

A 50.1-Mpixel 14-Bit 250-frames/s Back-Illuminated Stacked CMOS Image Sensor With Column-Parallel kT/C-Canceling SH and ΔΣADC

Authors: Chihiro Okada, Golan Zeituni, Koushi Uemura, Luong Hung, Kouji Matsuura, Takashi Moue, Kazutoshi Kodama, Masafumi Okano, Takafumi Morikawa, Kazuyoshi Yamashita, Osamu Oka, Yoshiaki Inada, Itai Shvartz, Ariel Benshem, Noam Eshel

A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits

Authors: Jongseok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juarez Hernandez, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano

Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC)

Authors: Robert Chen-Hao Chang, Wei-Zen Chen, Jun Deguchi

A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction

Authors: Mitsuya Fukazawa, Takashi Oshima, Masaki Fujiwara, Katsuki Tateyama, Atsushi Ochi, Alsubaie Raed, Tetsuo Matsui

GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation

Authors: Sanghoon Kang, Donghyeon Han, Juhyoung Lee, Dongseok Im, Sangyeob Kim, Soyeon Kim, Junha Ryu, Hoi-Jun Yoo

Ku-Band 70-/30-W-Class Internally Matched GaN Power Amplifiers With Low IMD3 Over a Wide Offset Frequency Range of Up To 400 MHz

Authors: Takaaki Yoshioka, Kenji Harauchi, Takumi Sugitani, Hiroaki Maehara, Takashi Yamasaki, Hiroaki Ichinohe, Miyo Miyashita, Kazuya Yamamoto, Seiki Goto

A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement

Authors: Kunyang Liu, Xinpeng Chen, Hongliang Pu, Hirofumi Shinohara

Structure-Reconfigurable Power Amplifier (SR-PA) and 0X/1X Regulating Rectifier for Adaptive Power Control in Wireless Power Transfer System

Authors: Fu-Bin Yang, Jonathan Fuh, Yu-Hsien Li, Makoto Takamiya, Po-Hung Chen

A 77-GHz 8RX3TX Transceiver for 250-m Long-Range Automotive Radar in 40-nm CMOS Technology

Authors: Tomoyuki Arai, Tatsunori Usugi, Tomotoshi Murakami, Shuya Kishimoto, Yoshiyuki Utagawa, Masato Kohtani, Ikuma Ando, Kazuhiro Matsunaga, Chihiro Arai, Shinji Yamaura

76- to 81-GHz CMOS Built-In Self-Test With 72-dB C/N and Less Than 1 ppm Frequency Tolerance for Multi-Channel Radar Applications

Authors: Masato Kohtani, Tomotoshi Murakami, Yoshiyuki Utagawa, Tomoyuki Arai, Shinji Yamaura

MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices

Authors: Christopher L. Ayala, Tomoyuki Tanaka, Ro Saito, Mai Nozoe, Naoki Takeuchi, Nobuyuki Yoshikawa

Introduction to the Special Issue on the 2020 Symposium on VLSI Circuits

Authors: Brian P. Ginsburg and Yusuke Oike

ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

Authors: Haidang Lin, Charlie Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Kulwant Brar, Nhat Nguyen, Shaishav Desai

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

Authors: Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems

Authors: Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, Ashbir Aviat Fadila, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Rui Wu, Yun Wang, Dongwon You, Bangan Liu, Zheng Sun, Yuncheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada

A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array

Authors: Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8 Time-Domain Latch Interpolation

Authors: Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka

A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS

Authors: Il-Min Yi, Naoki Miura, Hideyuki Nosaka

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

Authors: Tsung-Yung Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li

A Bluetooth 5 Transceiver With a Phase-Tracking RX and Its Corresponding Digital Baseband in 40-nm CMOS

Authors: Ming Ding, Peng Zhang, Yuming He, Stefano Traferro, Minyoung Song, Hannu Korpela, Kenichi Shibata, Keisuke Ueda, Yao-Hong Liu, Christian Bachmann

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)

Authors: Friedel Gerfers, Ping-Hsuan Hsieh, Dejan Markovic, Jun Deguchi, Eric Karl

10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture

Authors: Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Kulwant Brar, Nhat Nguyen, Shaishav Desai

A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs

Authors: Toshiyuki Kouchi, Mami Kakoi, Noriyasu Kumazaki, Akio Sugahara, Akihiro Imamoto, Yasufumi Kajiyama, Yuri Terada, Sanad Bushnaq, Naoaki Kanagawa, Takuyo Kodama, Ryo Fukuda, Hiromitsu Komai, Norichika Asaoka, Hidekazu Ohnishi, Ryosuke Isomura, Takaya Handa, Kensuke Yamamoto, Yuki Ishizaki, Yoko Deguchi, Atsushi Okuyama, Junichi Sato, Hiroki Yabe, Cynthia Hsu, Masahiro Yoshihara

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions

Authors: Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura

NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution

Authors: Jongsoo Lee, Jae-Yeol Han, Chilun Lo, Jongmi Lee, Wan Kim, Seungjin Kim, Byoungjoong Kang, Juyoung Han, Sangdon Jung, Takahiro Nomiyama, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang

A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving -96.4-dBm Sensitivity and -27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets

Authors: Masahisa Tamura, Hideyuki Takano, Hironori Nakahara, Hiroaki Fujita, Naoya Arisaka, Satoru Shinke, Norihito Suzuki, Yutaka Nakada, Yusuke Shinohe, Shinichirou Etou, Tetsuya Fujiwara, Fumitaka Kondo, Ken Yamamoto, Tomohiro Matsumoto, Yasushi Katayama

An Automotive LiDAR SoC for 240 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based AFE

Authors: Satoshi Kondo, Hiroshi Kubota, Hisaaki Katagiri, Yutaka Ota, Masatoshi Hirono, Tuan Thanh Ta, Hidenori Okuni, Shinichi Ohtsuka, Yoshinari Ojima, Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka, Katsuyuki Kimura, Akihide Sai, Nobu Matsumoto

Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC)

Authors: Atsushi Kawasumi, Mototsugu Hamada, Po-Hung Chen

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices

Authors: Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing

Authors: Shun Suzuki, Hiroki Aihara, Ken Takeuchi

A 22-ng/ $\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques

Authors: Yuki Furubayashi, Takashi Oshima, Taizo Yamawaki, Keiki Watanabe, Keijiro Mori, Naoki Mori, Akira Matsumoto, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi

300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers

Authors: Hiroshi Hamada, Takuya Tsutsumi, Hideaki Matsuzaki, Takuya Fujimura, Ibrahim Abdo, Atsushi Shirane, Kenichi Okada, Go Itami, Ho-Jin Song, Hiroki Sugiyama, Hideyuki Nosaka

A Beyond-1-Tb/s Coherent Optical Transmitter Front-End Based on 110-GHz-Bandwidth 2: 1 Analog Multiplexer in 250-nm InP DHBT

Authors: Munehiko Nagatani, Hitoshi Wakita, Hiroshi Yamazaki, Yoshihiro Ogiso, Miwa Mutoh, Minoru Ida, Fukutaro Hamaoka, Masanori Nakamura, Takayuki Kobayashi, Yutaka Miyamoto, Hideyuki Nosaka

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR

Authors: Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Bangan Liu, Aravind Tharayil Narayanan, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Keiichi Motoi, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada

A Feedforward Noise Reduction Technique in Capacitive MEMS Accelerometer Analog Front-End for Ultra-Low-Power IoT Applications

Authors: Ippei Akita, Takayuki Okazawa, Yoshihiko Kurui, Akira Fujimoto, Takashi Asano

A 373-F2 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and ${V}_{\text{SS}}$ Bias-Based Dark-Bit Detection

Authors: Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara

Millimeter-Scale Node-to-Node Radio Using a Carrier Frequency-Interlocking IF Receiver for a Fully Integrated 4 $\times$ 4 $\times$ 4 mm3 Wireless Sensor Node

Authors: Li-Xuan Chuo, Zhen Feng, Yejoong Kim, Nikolaos Chiotellis, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Anthony Grbic, David D. Wentzloff, David T. Blaauw, Hun-Seok Kim

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS

Authors: Yun Wang, Rui Wu, Jian Pang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Xi Fu, Daiki Matsumoto, Takeshi Nakamura, Ryo Kubozoe, Masaru Kawabuchi, Bangan Liu, Haosheng Zhang, Junjun Qiu, Hanli Liu, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada

Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits

Authors: Ken Takeuchi and Brian P. Ginsburg

A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques

Authors: Yang-Hang Fan, Ankur Kumar, Takayuki Iwai, Ashkan Roshan-Zamir, Shengchang Cai, Bo Sun, Samuel Palermo

A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator

Authors: Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon

A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D

Authors: Hiroyuki Kondo, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Noriaki Sakamoto, Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Kosuke Yayama

A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation

Authors: Jeongsup Lee, Satoru Miyoshi, Masaru Kawaminami, David T. Blaauw, Dennis Sylvester, Yiqun Zhang, Qing Dong, Wootaek Lim, Mehdi Saligane, Yejoong Kim, Seokhyeon Jeong, Jongyup Lim, Makoto Yasuda

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology

Authors: Noboru Shibata, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, Junji Musha, Takatoshi Minamoto, Kazushige Kanda, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Masatsugu Ogawa, Yusuke Ochi, Takahiro Shimizu, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Jun Nakai, Jumpei Sato, Namasivayam Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, Hiroshi Nakamura, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Tomoaki Nakano

A 2 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

Authors: Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications

Authors: Yutaka Yamada, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda

A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier

Authors: Ahmed ElShater, Praveen Kumar Venkatachala, Calvin Yoji Lee, Jason Muhlestein, Spencer Leuenberger, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon

An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver

Authors: Sangyeop Lee, Shinsuke Hara, Takeshi Yoshida, Shuhei Amakawa, Ruibing Dong, Akifumi Kasamatsu, Junji Sato, Minoru Fujishima

A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

Authors: Hanli Liu, Atsushi Shirane, Kenichi Okada, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya

A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth

Authors: Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx

A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO

Authors: Chintan Thakkar, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper

A 47.14-W 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications

Authors: Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

A Modular, Direct Time-of-Flight Depth Sensor in 45/65-nm 3-D-Stacked CMOS Technology

Authors: Augusto Ronchini Ximenes, Preethi Padmanabhan, Myung-Jae Lee, Yuichiro Yamashita, Dun-Nian Yaung, Edoardo Charbon

ULPAC: A Miniaturized Ultralow-Power Atomic Clock

Authors: Haosheng Zhang, Hans Herdian, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shigeyoshi Goka, Shinya Yanagimachi, Kenichi Okada

A 0.25-27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis

Authors: Yoshihide Komatsu, Akinori Shinmyo, Shuji Kato, Masami Funabashi, Kazuya Hatooka, Mayuko Fujita, Kenji Tanaka, Aoi Yamasaki, Kouichi Fukuda

An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators

Authors: Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Shigeru Maya, Akihide Sai, Kohei Onizuka

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Authors: Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi, Meng-Fan Chang

Single-Chip 3072-Element-Channel Transceiver/128-Subarray-Channel 2-D Array IC With Analog RX and All-Digital TX Beamformer for Echocardiography

Authors: Yutaka Igarashi, Shinya Kajiyama, Yusaku Katsube, Takuma Nishimoto, Tatsuo Nakagawa, Yasuyuki Okuma, Yohei Nakamura, Takahide Terada, Taizo Yamawaki, Toru Yazaki, Yoshihiro Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka

5-31-Hz 188- $\mu$ W Light-Sensing Oscillator With Two Active Inductors Fully Integrated on Plastic

Authors: Tilo Meister, Koichi Ishida, Stefan Knobelspies, Giuseppe Cantarella, Niko Mnzenrieder, Gerhard Trster, Corrado Carta, Frank Ellinger

A Sub-100 $\mu$ m-Range-Resolution Time-of-Flight Range Image Sensor With Three-Tap Lock-In Pixels, Non-Overlapping Gate Clock, and Reference Plane Sampling

Authors: Keita Yasutomi, Yushi Okura, Keiichiro Kagawa, Shoji Kawahito

A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC

Author: Kenichi Ohhata

3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition

Authors: Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa, Ken Takeuchi

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

Authors: Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada

A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

Authors: Jian Pang, Rui Wu, Yun Wang, Masato Dome, Hisashi Kato, Hongye Huang, Aravind Tharayil Narayanan, Hanli Liu, Bangan Liu, Takeshi Nakamura, Takuya Fujimura, Masaru Kawabuchi, Ryo Kubozoe, Tsuyoshi Miura, Daiki Matsumoto, Zheng Li, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada

A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS

Authors: Yun Wang, Bangan Liu, Rui Wu, Hanli Liu, Aravind Tharayil Narayanan, Jian Pang, Ning Li, Toru Yoshioka, Yuki Terashima, Haosheng Zhang, Dexian Tang, Makihiko Katsuragi, Daeyoung Lee, Sung Tae Choi, Kenichi Okada, Akira Matsuzawa

A Time-Resolved NIR Lock-In Pixel CMOS Image Sensor With Background Cancelling Capability for Remote Heart Rate Detection

Authors: Chen Cao, Yuya Shirakawa, Leyi Tan, Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Sung-Wook Jun, Tomohiko Kosugi, Satoshi Aoyama, Nobukazu Teranishi, Norimichi Tsumura, Shoji Kawahito

Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits

Authors: Ken Chang and Ken Takeuchi

A 12-Bit 31.1- $\mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance

Authors: Junhua Shen, Akira Shikata, Anping Liu, Baozhen Chen, Frederick Chalifoux

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems

Authors: Yuta Tsubouchi, Daisuke Miyashita, Takashi Toi, Yuji Satoh, Fumihiko Tachibana, Junji Wadatsumi, Makoto Morimoto, Ryuichi Fujimoto, Jun Deguchi

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System

Authors: Yongpan Liu, Fang Su, Yixiong Yang, Zhibo Wang, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Huazhong Yang

Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories

Authors: Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi

A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS

Authors: Ashkan Roshan-Zamir, Takayuki Iwai, Yang-Hang Fan, Ankur Kumar, Hae-Woong Yang, Lee Sledjeski, John Hamilton, Soumya Chandramouli, Arlo Aude, Samuel Palermo

An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage

Authors: Teruki Someya, A. K. M. Mahfuzul Islam, Takayasu Sakurai, Makoto Takamiya

A 7T-SRAM With Data-Write Technique by Capacitive Coupling

Authors: Daisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino

Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC)

Authors: Yohan Frans, Wim Dehaene, Masato Motomura, Seung-Jun Bae

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS

Authors: Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS

Authors: Kaushik Dasgupta, Saeid Daneshgar, Chintan Thakkar, Shinwon Kang, Anandaroop Chakrabarti, Shuhei Yamada, Nathan Narevsky, Debabani Choudhury, James E. Jaussi, Bryan Casper

An 802.11ax 4 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer

Authors: Shusuke Kawai, Rui Ito, Kengo Nakata, Yutaka Shimizu, Motoki Nagata, Tomohiko Takeuchi, Hiroyuki Kobayashi, Katsuyuki Ikeuchi, Takayuki Kato, Yosuke Hagiwara, Yuki Fujimura, Kentaro Yoshioka, Shigehito Saigusa, Hiroshi Yoshida, Makoto Arai, Toshiyuki Yamagishi, Hirotsugu Kajihara, Kazuhisa Horiuchi, Hideki Yamada, Tomoya Suzuki, Yuki Ando, Kensuke Nakanishi, Koichiro Ban, Masahiro Sekiya, Yoshimasa Egashira, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Authors: Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, Kenichi Okada

A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications

Authors: Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada

A 60-GHz 144-Element Phased-Array Transceiver for Backhaul Application

Authors: Tirdad Sowlati, Saikat Sarkar, Bevin George Perumana, Wei Liat Chan, Anna Papio Toda, Bagher Afshar, Michael Boers, Donghyup Shin, Timothy Mercer, Wei-Hong Chen, Alfred Grau Besoli, Seunghwan Yoon, Sissy Kyriazidou, Phil Yang, Vipin Aggarwal, Nooshin Vakilian, Dmitriy Rozenblit, Masoud Kahrizi, Joy Zhang, Alan Wang, Padmanava Sen, David Murphy, Ali Sajjadi, Alireza Tarighat Mehrabani, Evangelos Kornaros, Khim Low, Koji Kimura, Vincent Roussel, Hongyu Xie, Venkat Kodavati

A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor

Authors: Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura

A 6.9-m Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC

Authors: Masaki Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, Katsumi Honda, Hidekazu Kikuchi, Takuya Wada, Yasunobu Kamikubo, Tsukasa Miura, Masahiko Nakamizo, Naoki Jyo, Ryo Hayashibara, Shinya Miyata, Satoshi Yamamoto, Yoshiyuki Ota, Hirotsugu Takahashi, Tadayuki Taura, Yusuke Oike, Keiji Tatani, Takayuki Ezaki, Teruo Hirayama

A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC

Authors: Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto

A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS

Authors: Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa

Write and Read Frequency-Based Word-Line Batch VTH Modulation for 2-D and 3-D-TLC NAND Flash Memories

Authors: Yoshiaki Deguchi, Shun Suzuki, Ken Takeuchi

Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor

Authors: Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

Authors: Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

A Time-Resolved Four-Tap Lock-In Pixel CMOS Image Sensor for Real-Time Fluorescence Lifetime Imaging Microscopy

Authors: Min-Woong Seo, Yuya Shirakawa, Yoshimasa Kawata, Keiichiro Kagawa, Keita Yasutomi, Shoji Kawahito

A 2.267-Gb/s, 93.7-pJ/bit Non-Binary LDPC Decoder With Logarithmic Quantization and Dual-Decoding Algorithm Scheme for Storage Applications

Authors: Yuta Toriyama and Dejan Markovic

A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-m SiGe BiCMOS Technology

Authors: Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Hideo Arimoto, Masaru Kokubo, Tatemi Ido

A CMOS Timer-Injector Integrated Circuit for Self-Powered Sensing of Time-of-Occurrence

Authors: Liang Zhou, Kenji Aono, Shantanu Chakrabartty

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Authors: Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin

Authors: Qing Dong, Supreet Jeloka, Mehdi Saligane, Yejoong Kim, Masaru Kawaminami, Akihiko Harada, Satoru Miyoshi, Makoto Yasuda, David T. Blaauw, Dennis Sylvester

An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors

Authors: Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita

Introduction to the Special Issue on the 2017 Symposium on VLSI Circuits

Authors: Makoto Ikeda and Ken Chang

320 240 Back-Illuminated 10-m CAPD Pixels for High-Speed Modulation Time-of-Flight CMOS Image Sensor

Authors: Yuichi Kato, Takuya Sano, Yusuke Moriyama, Shunji Maeda, Takeshi Yamazaki, Atsushi Nose, Kimiyasu Shiina, Yohtaro Yasu, Ward van der Tempel, Alper Ercan, Yoshiki Ebiko, Daniel Van Nieuwenhove, Shunichi Sukegawa

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

Authors: Junhua Shen, Akira Shikata, Lalinda Fernando, Ned Guthrie, Baozhen Chen, Mark Maddox, Nikhil Mascarenhas, Ron Kapusta, Michael C. W. Coln

A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture

Authors: Tomohiro Takahashi, Yuichi Kaji, Yasunori Tsukuda, Shinichiro Futami, Katsuhiko Hanzawa, Takahito Yamauchi, Ping Wah Wong, Frederick T. Brady, Phil Holden, Thomas Ayers, Kyohei Mizuta, Susumu Ohki, Keiji Tatani, Hayato Wakabayashi, Yoshikazu Nitta

A Miniaturized Single-Transducer Implantable Pressure Sensor With Time-Multiplexed Ultrasonic Data and Power Links

Authors: Marcus J. Weber, Yoshiaki Yoshihara, Ahmed Sawaby, Jayant Charthad, Ting Chia Chang, Amin Arbabian

A 3.2 ppm/°C Second-Order Temperature Compensated CMOS On-Chip Oscillator Using Voltage Ratio Adjusting Technique

Authors: Guoqiang Zhang, Kosuke Yayama, Akio Katsushima, Takahiro Miki

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

Authors: Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR

Authors: Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi

A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers

Authors: Qiwei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone

A 13.56-MHz Wireless Power Transfer System With Enhanced Load-Transient Response and Efficiency by Fully Integrated Wireless Constant-Idle-Time Control for Biomedical Implants

Authors: Cheng Huang, Toru Kawajiri, Hiroki Ishikuro

Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference

Authors: Keith A. Bowman, Muhammad M. Khellah, Takashi Kono, Joseph Shor, Pui-In Mak

A 1.8e-rms Temporal Noise Over 110-dB-Dynamic Range 3.4µm Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter

Authors: Masahiro Kobayashi, Yusuke Onuki, Kazunari Kawabata, Hiroshi Sekine, Toshiki Tsuboi, Takashi Muto, Takeshi Akiyama, Yasushi Matsuno, Hidekazu Takahashi, Toru Koizumi, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue, Takeshi Ichikawa

A 2.1-Mpixel Organic Film-Stacked RGB-IR Image Sensor With Electrically Controllable IR Sensitivity

Authors: Shin'ichi Machida, Sanshiro Shishido, Takeyoshi Tokuhara, Masaaki Yanagida, Takayoshi Yamada, Masumi Izuchi, Yoshiaki Sato, Yasuo Miyake, Manabu Nakata, Masashi Murakami, Mitsuru Harada, Yasunori Inoue

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

Authors: Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi

A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD

Authors: Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan

A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture

Authors: Shunta Iguchi, Takayasu Sakurai, Makoto Takamiya

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

Authors: Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC

Authors: Takuji Miki, Toshiaki Ozeki, Jun-ichi Naka

A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing

Authors: Daisuke Miyashita, Shouhei Kousai, Tomoya Suzuki, Jun Deguchi

A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme

Authors: Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Yi-Ju Chen, Hiroyuki Yamauchi

A 76- to 81-GHz Multi-Channel Radar Transceiver

Authors: Takeji Fujibayashi, Yohsuke Takeda, Weihu Wang, Yi-Shin Yeh, Willem Stapelbroek, Seiji Takeuchi, Brian A. Floyd

A Compact Broadband Mixed-Signal Power Amplifier in Bulk CMOS With Hybrid Class-G and Dynamic Load Trajectory Manipulation

Authors: Song Hu, Shouhei Kousai, Hua Wang

A 1-3 GHz Delta-Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI

Authors: Hamed Gheidi, Toshifumi Nakatani, Vincent W. Leung, Peter M. Asbeck

A 58-nm 2-Gb MLC "B4-Flash" Memory with Flexible Multisector Architecture

Authors: Taku Ogura, Yasushi Kasa, Kazuhide Kurosaki, Mitsuhiro Tomoeda, Hisakazu Otoi, Satoshi Shimizu, Masafumi Katsumata, Natsuo Ajika, Kazuo Kobayashi

Introduction to the Special Issue on the 2016 Symposium on VLSI Circuits

Authors: Brian P. Ginsburg and Makoto Ikeda

A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique

Authors: Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu

8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration

Authors: Yusuke Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito Sakano, Yoshiaki Kitano, Takuya Nakamura, Takayuki Toyama, Hayato Iwamoto, Takayuki Ezaki

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS

Authors: Tatsuya Onuki, Wataru Uesugi, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, J. Y. Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki

A 0.5-9.5-GHz, 1.2-s Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling

Authors: Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

Electronic-Photonic Integrated Circuit for 3D Microimaging

Authors: Behnam Behroozpour, Phillip A. M. Sandborn, Niels Quack, Tae Joon Seok, Yasuhiro Matsui, Ming C. Wu, Bernhard E. Boser

A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard

Authors: Shinichi Shibahara, Chikafumi Takahashi, Kazuki Fukuoka, Yuko Kitaji, Takahiro Irita, Hirotaka Hara, Yasuhisa Shimazaki, Jun Matsushima

Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference

Authors: Dennis Sylvester, Dejan Markovic, Roman Genov, Atsushi Kawasumi, Subhasish Mitra

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

Authors: Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

Authors: Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Richard Schreier, Qingdong Meng, Jos B. Silva, Donald Paterson, Jeffrey C. Gealow

A 300 GHz CMOS Transmitter With 32-QAM 17.5 Gb/s/ch Capability Over Six Channels

Authors: Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Shinsuke Hara, Akifumi Kasamatsu, Koichi Mizuno, Kazuaki Takahashi, Takeshi Yoshida, Minoru Fujishima

A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture

Authors: Takashi Masuda, Ryota Shinoda, Jeremy Chatwin, Jacob Wysocki, Koki Uchino, Yoshifumi Miyajima, Yosuke Ueno, Kenichi Maruko, Zhiwei Zhou, Hideyuki Suzuki, Norio Shoji

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

Authors: Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura

CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water With 120 and 60 GHz Oscillator Arrays

Authors: Takeshi Mitsunaka, Daiki Sato, Nobuyuki Ashida, Akira Saito, Kunihiko Iizuka, Tetsuhito Suzuki, Yuichi Ogawa, Minoru Fujishima

Introduction to the Special Section on the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Authors: Makoto Ikeda and Noriyuki Miura

Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications

Authors: Tomoya Ishii, Sheyang Ning, Masahiro Tanaka, Kota Tsurumi, Ken Takeuchi

An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise

Authors: Masahiko Maruyama, Shigenari Taguchi, Masafumi Yamanoue, Kunihiko Iizuka

Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting

Authors: Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC

Authors: Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers

Authors: Lilan Yu, Masaya Miyahara, Akira Matsuzawa

A 5.6 nV/ √Hz Chopper Operational Amplifier Achieving a 0.5 μV Maximum Offset Over Rail-to-Rail Input Range With Adaptive Clock Boosting Technique

Author: Yoshinori Kusuda

A 25 3 μW at 60 fps 240 × 160 Pixel Vision Sensor for Motion Capturing With In-Pixel Nonvolatile Analog Memory Using CAAC-IGZO FET

Authors: Takuro Ohmaru, Takashi Nakagawa, Shuhei Maeda, Yuki Okamoto, Munehiro Kozuma, Seiichi Yoneda, Hiroki Inoue, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Shunpei Yamazaki

A Near-Optimum 13.56 MHz CMOS Active Rectifier With Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants

Authors: Cheng Huang, Toru Kawajiri, Hiroki Ishikuro

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Authors: Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi

A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

Authors: Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa

12.5 Gb/s Optical Driver and Receiver ICs With Double-Threshold AGC for SATA Out-of-Band Transmission

Authors: Hiroshi Uemura, Yoichiro Kurita, Hideto Furuyama

A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver

Authors: Atsutake Kosuge, Junichiro Kadomoto, Tadahiro Kuroda

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

Authors: Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad

Authors: Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa

An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories

Authors: Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi

Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits

Authors: Masato Motomura and Andreia Cathelin

High-level Video Analytics PC Subsystem Using SoC With Heterogeneous Multicore Architecture

Authors: Yukihiro Sasagawa and Atsuhiro Mori

A Broadband Mixed-Signal CMOS Power Amplifier With a Hybrid Class-G Doherty Efficiency Enhancement Technique

Authors: Song Hu, Shouhei Kousai, Hua Wang

Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster

Authors: Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya

A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process

Authors: Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, George L. Geannopoulos, Jonathan Douglas, Nasser A. Kurd

Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference

Authors: Edith Beign, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

Authors: Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology

Authors: Mario Sako, Yoshihisa Watanabe, Takao Nakajima, Jumpei Sato, Kazuyoshi Muraoka, Masaki Fujiu, Fumihiro Kono, Michio Nakagawa, Masami Masuda, Koji Kato, Yuri Terada, Yuki Shimizu, Mitsuaki Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto, Masahiro Kamoshida, Masatoshi Kohno, Yoshinao Suzuki, Tomoharu Hashiguchi, Tsukasa Kobayashi, Masashi Yamaoka, Ryuji Yamashita

A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging

Authors: Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Yoshimasa Kawata, Nobukazu Teranishi, Zhuo Li, Izhal Abdul Halin, Shoji Kawahito

A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C

Authors: Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

Authors: Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno

A 60 V Auto-Zero and Chopper Operational Amplifier With 800 kHz Interleaved Clocks and Input Bias Current Trimming

Author: Yoshinori Kusuda

RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter

Authors: Atsushi Shirane, Yiming Fang, Haowei Tan, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Jussi Ryynnen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference

Authors: Makoto Takamiya, Jieh-Tsorng Wu, Jussi Ryynnen, Kenichi Okada, Jaeha Kim

A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS

Authors: Bo Zhang, Karapet Khanoyan, Hamid Hatamkhani, Haitao Tong, Kangmin Hu, Siavash Fallahi, Mohammed M. Abdul-Latif, Kambiz Vakilian, Ichiro Fujimori, Anthony Brewster

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring

Authors: Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

A 1 mm Pitch 80 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan

Authors: Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Authors: Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki

A Reference-Less Single-Loop Half-Rate Binary CDR

Authors: Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

Authors: Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx

Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC)

Authors: Angelo Nagari, Kenichi Okada, Marian Verhelst

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Authors: James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

Authors: Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho

Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS

Authors: Song Hu, Shouhei Kousai, Jong Seok Park, Outmane Lemtiri Chlieh, Hua Wang

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

Authors: Ryu Ogiwara, Daisaburo Takashima, Sumiko M. Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga

Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits

Authors: Jeffrey C. Gealow and Masato Motomura

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Authors: Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

Authors: Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit

Authors: Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Fukashi Morishita

Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC

Authors: Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro

Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process

Authors: Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, Dror Zilberman

Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range"

Authors: Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction

Authors: Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

Authors: Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa

Integrated Line Driver for Digital Pulse-Width Modulation Driven AMOLED Displays on Flex

Authors: Jan Genoe, Koji Obata, Marc Ameys, Kris Myny, Tung Huei Ke, Manoj Nag, Soeren Steudel, Sarah Schols, Joris Maas, Ashutosh Tripathi, Jan-Laurens P. J. van der Steen, Tim Ellis, Gerwin H. Gelinck, Paul Heremans

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

Authors: Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

Authors: Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

A 143 81 Mutual-Capacitance Touch-Sensing Analog Front-End With Parallel Drive and Differential Sensing Architecture

Authors: Masayuki Miyamoto, Mutsumi Hamaguchi, Akira Nagao

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

Authors: Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong

Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier

Authors: Shouhei Kousai, Kohei Onizuka, Junji Wadatsumi, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka

Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC)

Authors: Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE

Authors: Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori

A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS

Authors: Hui Pan, Yuan Yao, Mostafa Hammad, Junhua Tan, Karim Abdelhalim, Evelyn Wenting Wang, Rick C. J. Hsu, Derek Tam, Ichiro Fujimori

A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving

Authors: Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka

A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver

Authors: Hideo Nakane, Ryuichi Ujiie, Takashi Oshima, Takaya Yamamoto, Keisuke Kimura, Yuichi Okuda, Kosuke Tsuiji, Tatsuji Matsuura

A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS

Authors: Xin Zhang, Po-Hung Chen, Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya

A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects

Authors: Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

Authors: Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, Akira Matsuzawa

A 12 Bit 1.6 GS/s BiCMOS 22 Hierarchical Time-Interleaved Pipeline ADC

Authors: Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Kenneth Maclean, Jake Hu, Mark Weaver, Matthew Gindlesperger, Scott Kaylor, Robert Payne, Charles K. Sestok, William Bright

A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks

Authors: Jiawei Xu, Srinjoy Mitra, Akinori Matsumoto, Shrishail Patki, Chris Van Hoof, Kofi A. A. Makinwa, Refet Firat Yazicioglu

Introduction to the Special Issue on the 2013 IEEE Custom Integrated Circuits Conference

Authors: Ken Suyama and Andrea Mazzanti

A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range

Authors: Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx

Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits

Authors: Hideyuki Kabuo and Jeffrey C. Gealow

1 Mb 0.41 m2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing

Authors: Jing Li, Robert K. Montoye, Masatoshi Ishii, Leland Chang

A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder

Authors: Dajiang Zhou, Jinjia Zhou, Gang He, Satoshi Goto

A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS

Authors: Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto

Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits

Authors: Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai

A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity

Authors: Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion

Authors: Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura

Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions

Authors: Timothy C. Fischer, Byeong-Gyu Nam, Leland Chang, Tadahiro Kuroda, Michiel A. P. Pertijs

The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server

Authors: Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Kinya Ishizaka, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada

40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C

Authors: Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi

A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler

Authors: Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda

A 130.7-mm2 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

Authors: Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Achal Kathuria, Vincent Lai, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Yibo Yin, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Hirofumi Inoue, Luca Fasoli

A 1024 8, 700-ps Time-Gated SPAD Line Sensor for Planetary Surface Exploration With Laser Raman Spectroscopy and LIBS

Authors: Yuki Maruyama, Jordana Blacksberg, Edoardo Charbon

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Authors: Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Authors: Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

A 0.18-m CMOS SoC for a 100-m-Range 10-Frame/s 200 96-Pixel Time-of-Flight Depth Sensor

Authors: Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Masaru Ogawa, Manabu Kagami

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

Authors: Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process

Authors: Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

Authors: Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi, Haiyang Zhu

A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage

Authors: Noriaki Saito, Takayuki Tsukizawa, Naganori Shirakata, Tadashi Morita, Koichiro Tanaka, Junji Sato, Yohei Morishita, Masaki Kanemaru, Ryo Kitamura, Takahiro Shima, Toshifumi Nakatani, Kenji Miyanaga, Tomoya Urushihara, Hiroyuki Yoshikawa, Takenori Sakamoto, Hiroyuki Motozuka, Yoshinori Shirakawa, Naoya Yosoku, Akira Yamamoto, Ryosuke Shiozaki, Koji Takinami

A High Voltage Self-Biased Integrated DC-DC Buck Converter With Fully Analog MPPT Algorithm for Electrostatic Energy Harvesters

Authors: Stefano Stanzione, Chris van Liempd, Rob van Schaijk, Yasuyuki Naito, Refet Firat Yazicioglu, Chris Van Hoof

A Blind Baud-Rate ADC-Based CDR

Authors: Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Design of a 300-mV 2.4-GHz Receiver Using Transformer-Coupled Techniques

Authors: Fan Zhang, Yasunori Miyahara, Brian P. Otis

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

Authors: Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM

Authors: Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer

A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS

Authors: Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs)

Authors: Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System

Authors: Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques

Authors: Meng-Fan Chang, Ming-Bin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

Authors: Minoru Fujishima, Mizuki Motoyoshi, Kosuke Katayama, Kyoya Takano, Naoko Ono, Ryuichi Fujimoto

Active Terahertz Imaging Using Schottky Diodes in CMOS: Array and 860-GHz Pixel

Authors: Ruonan Han, Yaming Zhang, Youngwan Kim, Dae Yeon Kim, Hisashi Shichijo, Ehsan Afshari, Kenneth K. O

A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy

Authors: Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits

Authors: Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters

Authors: Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon

0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration

Authors: Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu

Introduction to the Special Issue on the IEEE 2012 Custom Integrated Circuits Conference

Authors: Ken Suyama and Hasnain Lakdawala

A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers

Authors: Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa

A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms

Authors: Meng-Fan Chang, Chih-Sheng Lin, Wei-Cheng Wu, Ming-Pin Chen, Yen-Huei Chen, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Cha-Hsin Lin, Hiroyuki Yamauchi

Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication"

Authors: Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

Authors: Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs

Authors: Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

A 70-100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link

Authors: Shahriar Shahramian, Yves Baeyens, Noriaki Kaneda, Young-Kai Chen

Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits

Authors: Vivek De and Hideyuki Kabuo

A 0.41 A Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

Authors: Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Authors: Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

Authors: Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Authors: Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi

A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver

Authors: Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Wendemagegnehu T. Beyene, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Inipodu Murugan, Kun-Yung Ken Chang, Xingchao Chuck Yuan

A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines

Authors: Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing

Authors: Wei Deng, Kenichi Okada, Akira Matsuzawa

A 100-m Range 10-Frame/s 340,x,96-Pixel Time-of-Flight Depth Sensor in 0.18-m CMOS

Authors: Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Satoru Kato, Manabu Kagami

Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement

Authors: Shu-Meng Yang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Bin Chen, Hiroyuki Yamauchi

Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits

Authors: Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai

A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface

Authors: Kazushige Kanda, Noboru Shibata, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, Naoki Kobayashi, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, Yasuhiko Honda, Yosuke Kato, Shingo Zaitsu, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

Authors: Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

Authors: Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Khoa Minh Nguyen, Hyung-Jin Lee, Ashoke Ravi, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Satish Venkatesan, Durgesh Srivastava, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Sunder Ramamurthy, Raj Yavatkar, Krishnamurthy Soumyanath

CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable Compressed Sensing

Authors: Yusuke Oike and Abbas El Gamal

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

Authors: Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference

Authors: Maurits Ortmanns, Timothy C. Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai

A Global-Shutter CMOS Image Sensor With Readout Speed of 1-Tpixel/s Burst and 780-Mpixel/s Continuous

Authors: Yasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, Rihito Kuroda, Hideki Mutoh, Ryuta Hirose, Hideki Tominaga, Kenji Takubo, Yasushi Kondo, Shigetoshi Sugawa

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link

Authors: Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan

Ring Amplifiers for Switched Capacitor Circuits

Authors: Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon

A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier

Authors: Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka

A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication

Authors: Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa

A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW

Authors: Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai

A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

Authors: Bob Verbruggen, Masao Iriguchi, Jan Craninckx

An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection

Authors: Po-Hung Chen, Xin Zhang, Koichi Ishida, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai

An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects

Authors: Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho

CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation

Authors: Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi

Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication

Authors: Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller

Authors: Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro

A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards

Authors: Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card

Authors: Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda

Compact, High Impedance and Wide Bandwidth Detectors for Characterization of Millimeter Wave Performance

Authors: Chikuang Yu, Chieh-Lin Wu, Sandeep Kshattry, Yang-Hun Yun, Choong-Yul Cha, Hisashi Shichijo, Kenneth K. O

Nonvolatile Memory With Extremely Low-Leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistor

Authors: Hiroki Inoue, Takanori Matsuzaki, Shuhei Nagatsuka, Yutaka Okazaki, Toshinari Sasaki, Kousei Noda, Daisuke Matsubayashi, Takahiko Ishizu, Tatsuya Onuki, Atsuo Isobe, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Jun Koyama, Shunpei Yamazaki

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

Authors: Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka

A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs

Authors: Kentaro Yamamoto and Anthony Chan Carusone

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

Authors: Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology

Authors: Marek Gersbach, Yuki Maruyama, Rahmadi Trimananda, Matthew W. Fishburn, David Stoppa, Justin A. Richardson, Richard Walker, Robert K. Henderson, Edoardo Charbon

NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD

Authors: Teruyoshi Hatanaka and Ken Takeuchi

Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping

Authors: Hans Jrgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide

A Push-Push VCO With 13.9-GHz Wide Tuning Range Using Loop-Ground Transmission Line for Full-Band 60-GHz Transceiver

Authors: Takahiro Nakamura, Toru Masuda, Katsuyoshi Washio, Hiroshi Kondoh

Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming

Authors: Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai

A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS

Authors: Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda

A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems

Authors: Masaki Kitsunezuka, Hiroshi Kodama, Naoki Oshima, Kazuaki Kunihiro, Tadashi Maeda, Muneo Fukaishi

Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications

Authors: Toshifumi Nakatani, Jeremy Rode, Donald F. Kimball, Lawrence E. Larson, Peter M. Asbeck

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

Authors: Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

Authors: Yen-Huei Chen, Shao-Yu Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, Hiroyuki Yamauchi

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines

Authors: Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

Authors: Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits

Authors: Makoto Nagata and Vivek De

A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS

Authors: Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs

Authors: Shinichiro Uemura, Yukio Hiraoka, Takayuki Kai, Shiro Dosho

A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique

Authors: Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno

An Embedded DRAM Technology for High-Performance NAND Flash Memories

Authors: Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii

A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology

Authors: Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Takeshi Ogawa, Toshiaki Edahiro, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Yuka Furuta, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Rieko Tanaka, Hiromitsu Komai, Mai Muramoto, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara

A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier

Authors: Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

Authors: Min-Woong Seo, Sungho Suh, Tetsuya Iida, Taishi Takasawa, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Keita Yasutomi, Shoji Kawahito

Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming

Authors: Shuhei Tanakamaru, Chinglin Hung, Ken Takeuchi

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference

Authors: Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS

Authors: Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune

A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect

Authors: Satoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Hiroyuki Yamagishi, Satoru Shinke, Kenji Komori, Masahiro Uno, Yoshiyuki Akiyama, Kenichi Kawasaki, Ali Hajimiri

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c

Authors: Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link

Authors: Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura

A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

Authors: Freeman Zhong, Shaolei Quan, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang

A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation

Authors: Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Authors: Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, Kazumasa Yanagisawa

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications

Authors: Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Authors: Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe

Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer

Authors: Omid Rajaee, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, Un-Ku Moon

A 30 Gb/s/Link 2.2 Tb/s/mm 2 Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface

Authors: Yasuhiro Take, Noriyuki Miura, Tadahiro Kuroda

A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter

Authors: Koji Takinami, Richard Strandberg, Paul C. P. Liang, Gregore Le Grand de Mercey, Tony Wong, Mahnaz Hassibi

Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing

Authors: Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai

Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers

Authors: Yiping Feng, Gaku Takemura, Shunji Kawaguchi, Nobuyuki Itoh, Peter R. Kinget

A Scalable Massively Parallel Processor for Real-Time Image Processing

Authors: Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jrgen Mattausch, Kazutami Arimoto

Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems

Authors: Munehiko Nagatani, Hideyuki Nosaka, Shogo Yamanaka, Kimikazu Sano, Koichi Murata

A 0.5 V Operation V TH Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems

Authors: Shuhei Tanakamaru and Ken Takeuchi

Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

Authors: Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi

Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells

Authors: Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs

Authors: Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama

A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers

Authors: Jonathan Borremans, Gunjan Mandal, Vito Giannini, Bjrn Debaillie, Mark Ingels, Tomohiro Sano, Bob Verbruggen, Jan Craninckx

A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique

Authors: Masanori Furuta, Mai Nozawa, Tetsuro Itakura

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD

Authors: Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi

A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver

Authors: Lechang Liu, Takayasu Sakurai, Makoto Takamiya

An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration

Authors: Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

Authors: Takushi Hashida and Makoto Nagata

A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme

Authors: Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Authors: Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs

Authors: Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi

A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5-20 GHz Tunable LC-VCO

Authors: Akira Tanabe, Ken'ichiro Hijioka, Hirokazu Nagase, Yoshihiro Hayashi

A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Authors: Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

Authors: Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto

A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme

Authors: Masaki Kitsunezuka, Takashi Tokairin, Tadashi Maeda, Muneo Fukaishi

A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell

Authors: Daisaburo Takashima, Yasushi Nagadomi, Tohru Ozaki

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance

Authors: Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

Authors: John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao

User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects

Authors: Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM

Authors: Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki

A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS

Authors: Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

Authors: Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito

A 5 mm2 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

Authors: Mark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Bjrn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx

A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization

Authors: Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe

A Millimeter-Wave Intra-Connect Solution

Authors: Kenichi Kawasaki, Yoshiyuki Akiyama, Kenji Komori, Masahiro Uno, Hidenori Takeuchi, Tomoari Itagaki, Yasufumi Hino, Yoshinobu Kawasaki, Katsuhisa Ito, Ali Hajimiri

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

Authors: Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi

A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers

Authors: Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe

0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

Authors: Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS

Authors: Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi

Phase Error Calibration Technique for Rotary Traveling Wave Oscillators

Authors: Koji Takinami and Rich Walsworth

Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives

Authors: Teruyoshi Hatanaka, Ryoji Yajima, Takeshi Horiuchi, Shouyu Wang, Xizhen Zhang, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi

A 120-145 GHz Heterodyne Receiver Chipset Utilizing the 140 GHz Atmospheric Window for Passive Millimeter-Wave Imaging Applications

Authors: Stefan Koch, Marc Guthoerl, Ingmar Kallfass, Arnulf Leuther, Shin Saito

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

Authors: Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing

Authors: Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda

A 0.13 m SiGe BiCMOS Technology Featuring fT/fmax of 240/330 GHz and Gate Delays Below 3 ps

Authors: Holger Rcker, Bernd Heinemann, Wolfgang Winkler, Rainer Barth, Johannes Borngrber, Jrgen Drews, Gerhard G. Fischer, Alexander Fox, Thomas Grabolla, Ulrich Haak, Dieter Knoll, Falk Korndrfer, Andreas Mai, Steffen Marschmeyer, Peter Schley, Detlef Schmidt, J. Schmidt, Markus Andreas Schubert, K. Schulz, Bernd Tillack, Dirk Wolansky, Yuji Yamamoto

A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins - Write/Read Assist Techniques for 1-V Operated Memory Cells

Authors: Nobutaro Shibata, Mayumi Watanabe, Hideomi Okiyama

Auto Correction Feedback for Ripple Suppression in a Chopper Amplifier

Author: Yoshinori Kusuda

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

Authors: Alexandre Siligaris, Yasuhiro Hamada, Christopher Mounet, Christine Raynaud, Baudouin Martineau, Nicolas Deparis, Nathalie Rolland, Muneo Fukaishi, Pierre Vincent

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

Authors: Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz

A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Authors: Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen, Yen-Hui Chen, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback

Authors: Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS

Authors: Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa

Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs

Authors: Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida

A 0.2 mm 2 , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability

Authors: Haruya Ishizaki and Masayuki Mizuno

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator

Authors: Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho, Akira Matsuzawa

A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications

Authors: Toshiya Mitomo, Naoko Ono, Hiroaki Hoshino, Yoshiaki Yoshihara, Osamu Watanabe, Ichiro Seto

A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture

Authors: Yuji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Norihito Kato, Tetsuya Matsumoto, Michio Yotsuyanagi

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Authors: Omid Rajaee, Tawfiq Musah, Nima Maghari, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, Un-Ku Moon

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

Authors: Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme

Authors: Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno

LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators

Authors: Yun-Shiang Shu, Junpei Kamiishi, Koji Tomioka, Koichi Hamashita, Bang-Sup Song

Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection

Authors: Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits

Authors: Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori

A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors

Authors: Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

Authors: Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

Authors: Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS

Authors: Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Masashi Kono, Tatsuya Saito

An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0

Authors: Francesco Gatta, Ray Gomez, Young J. Shin, Takayuki Hayashi, Hanli Zou, James Y. C. Chang, Leonard Dauphinee, Jianhong Xiao, Dave S.-H. Chang, Tai-Hong Chih, Massimo Brandolini, Dongsoo Koh, Bryan Juo-Jung Hung, Tao Wu, Mattia Introini, Giuseppe Cusmai, Ertan Zencir, Frank Singor, Hans Eberhart, Loke Kun Tan, Bruce Currivan, Lin He, Peter Cangiane, Pieter Vorenkamp

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

Authors: Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

Authors: Shunichi Kaeriyama, Yasushi Amamiya, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

Authors: Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement

Authors: Shouhei Kousai and Ali Hajimiri

A Charge-Multiplication CMOS Image Sensor Suitable for Low-Light-Level Imaging

Authors: Ryu Shimizu, Mamoru Arimoto, Hayato Nakashima, Kaori Misawa, Toshikazu Ohno, Yugo Nose, Keisuke Watanabe, Tatsushi Ohyama

A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery

Authors: Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

Authors: Koji Kotani, Atsushi Sasaki, Takashi Ito

A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications

Authors: Tatsuya Mori, Yasuyuki Ueda, Nobuhiro Nonogaki, Toshihiro Terazawa, Milosz Sroka, Tetsuya Fujita, Takeshi Kodaka, Takayuki Mori, Kumiko Morita, Hideho Arakida, Takashi Miura, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture

Authors: Kenichi Ohhata, Koki Uchino, Yuichiro Shimizu, Kosuke Oyama, Kiichi Yamashita

ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier

Authors: Bipul C. Paul, Shinobu Fujita, Masaki Okajima

Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors

Authors: Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu

A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-m CMOS

Authors: Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro

A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators

Author: Mamoru Sasaki

Intermittent Operation Control Scheme for Reducing Power Consumption of UWB-IR Receiver

Authors: Takahide Terada, Ryosuke Fujiwara, Goichi Ono, Takayasu Norimatsu, Tatsuo Nakagawa, Masayuki Miyazaki, Kei Suzuki, Kazuo Yano, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura

A Fifth-Order Gm-C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range

Authors: Yusuke Aiba, Koji Tomioka, Yuta Nakashima, Koichi Hamashita, Bang-Sup Song

A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

Authors: Masaki Kitsunezuka, Shinichi Hori, Tadashi Maeda

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback

Authors: Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications

Authors: Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

Authors: Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

Authors: Alexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu

A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

Authors: Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS

Authors: Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo R, Kunihiko Iizuka

All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

Authors: Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 m CMOS

Authors: Yiping Feng, Gaku Takemura, Shunji Kawaguchi, Peter R. Kinget

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs

Authors: Yen-Huei Chen, Gary Chan, Shao-Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi

A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS

Authors: Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe

A Sub-s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support

Authors: Kenichi Kawasaki, Tetsuyoshi Shiota, Koichi Nakayama, Atsuki Inoue

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

Authors: Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer

A 0.7 V Single-Supply SRAM With 0.495 m2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

Authors: Keiichi Kushida, Azuma Suzuki, Gou Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, Takahiko Sasaki, Akira Katayama, Yuki Fujimura, Tomoaki Yabe

Introduction to the Special Issue on the 2008 Symposium on VLSI Circuits

Authors: Katsu Nakamura and Masayuki Mizuno

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

Author: Ken Takeuchi

A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

Authors: Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver

Authors: Kyehyung Lee, Qingdong Meng, Tetsuro Sugimoto, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Un-Ku Moon, Gabor C. Temes

A High-Speed Inductive-Coupling Link With Burst Transmission

Authors: Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

Authors: Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

Authors: Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga

A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna

Authors: Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro, Tadahiro Kuroda

A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection

Authors: Nobuo Sasaki, Kentaro Kimoto, Wataru Moriyama, Takamaro Kikkawa

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology

Authors: Raul Cernea, Long Pham, Farookh Moogat, Siu Lung Chan, Binh Le, Yan Li, Shouchang Tsao, Taiyuan Tseng, Khanh Nguyen, Jason Li, Jayson Hu, Jonghak Yuh, Cynthia Hsu, Fanglin Zhang, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, Jeffrey Lutze, Yingda Dong, Masaaki Higashitani, Junhui Yang, Hung-Szu Lin, Vamshi Sakhamuri, Alan Li, Feng Pan, Sridhar Yadala, Subodh Taigor, Kishan Pradhan, James Lan, Jim Chan, Takumi Abe, Yasuyuki Fukuda, Hideo Mukai, Koichi Kawakami, Connie Liang, Tommy Ip, Shu-Fen Chang, Jaggi Lakshmipathi, Sharon Huynh, Dimitris Pantelakis, Mehrdad Mofidi, Khandker Quader

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference

Authors: Donhee Ham, Hideto Hidaka, Ron Ho, Ram K. Krishnamurthy

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

Authors: Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama

Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor

Authors: Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

Authors: Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jongmin Park, Tapan Samaddar, Hao Nguyen, Man Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Yero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, Jim Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul-Adrian Cernea, Sharon Huynh, Dimitris Pantelakis, Chi-Ming Wang, Khandker Quader

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Authors: Ichiro Aoki, Scott D. Kee, Rahul Magoon, Roberto Aparicio, Florian Bohn, Jeff Zachan, Geoff Hatcher, Donald McClymont, Ali Hajimiri

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR

Authors: Kyehyung Lee, Jeongseok Chae, Mitsuru Aniya, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Gabor C. Temes

A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback

Authors: Hidemi Noguchi, Nobuhide Yoshida, Hiroaki Uchida, Manabu Ozaki, Shunichi Kanemitsu, Shigeki Wada

A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC

Authors: Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference

Authors: Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee

Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time

Authors: David Levacq, Makoto Takamiya, Takayasu Sakurai

A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS

Authors: Seiji Mochizuki, Tetsuya Shibayama, Masaru Hase, Fumitaka Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, Hiroshi Ueda, Kazuyuki Ishikawa, Hiromi Watanabe

A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array

Authors: Yoichi Yoshida, Noriyuki Miura, Tadahiro Kuroda

A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS

Authors: Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto, Takahiro Miki

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

Authors: Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu

A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR

Authors: Kentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson

A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling

Authors: Takaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura

A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors

Authors: Noriko Ide, Woonghee Lee, Nana Akahane, Shigetoshi Sugawa

An Assessment of -Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

Authors: Nitz Saputra, Mina Danesh, Alessandro Baiano, Ryoichi Ishihara, John R. Long, Nobuo Karaki, Satoshi Inoue

Gaussian Monocycle Pulse Transmitter Using 0.18 m CMOS Technology With On-Chip Integrated Antennas for Inter-Chip UWB Communication

Authors: Takamaro Kikkawa, Pran Kanai Saha, Nobuo Sasaki, Kentaro Kimoto

A 200-V/e- CMOS Image Sensor With 100-ke- Full Well Capacity

Authors: Satoru Adachi, Woonghee Lee, Nana Akahane, Hiromichi Oshikubo, Koichi Mizobuchi, Shigetoshi Sugawa

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

Authors: Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations

Authors: Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

Authors: Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu

Memory at VLSI Circuits Symposium

Authors: Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi

A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications

Authors: Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

Authors: Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto

A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System

Authors: Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho

A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer

Authors: Toshiya Mitomo, Ryuichi Fujimoto, Naoko Ono, Ryoichi Tachibana, Hiroaki Hoshino, Yoshiaki Yoshihara, Yukako Tsutsumi, Ichiro Seto

1-cc Computer: Cross-Layer Integration With UWB-IR Communication and Locationing

Authors: Tatsuo Nakagawa, Goichi Ono, Ryosuke Fujiwara, Takayasu Norimatsu, Takahide Terada, Masayuki Miyazaki, Kei Suzuki, Kazuo Yano, Yuji Ogata, Akira Maeki, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura

A 0.016 mm2, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis

Authors: Koichi Nose and Masayuki Mizuno

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

Authors: Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, Kiyoaki Iwasa, Michio Nakagawa, Masaki Fujiu, Takahiro Shimizu, Mitsuaki Honma, Satoru Hoshi, Toshimasa Kawaai, Kazunori Kanebako, Susumu Yoshikawa, Hideyuki Tabata, Atsushi Inoue, Toshiyuki Takahashi, Toshifumi Shano, Yukio Komatsu, Katsushi Nagaba, Mitsuhiko Kosakai, Noriaki Motohashi, Kazuhisa Kanazawa, Kenichi Imamiya, Hiroto Nakai, Menahem Lasser, Mark Murin, Avraham Meir, Arik Eyal, Mark Shlick

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding

Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Introduction to the Special Issue on the 2007 Symposium on VLSI Circuits

Authors: Kazuo Yano and Katsu Nakamura

Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects

Authors: Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range

Authors: Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

ΔΣ PLL Transmitter With a Loop-Bandwidth Calibration System

Authors: Yukinori Akamine, Manabu Kawabe, Kazuyuki Hori, Takao Okazaki, Masumi Kasahara, Satoshi Tanaka

A Programmable Impedance Matching Circuit for Voiceband Modems

Authors: Russell A. Hershbarger, Wenyan Jia, Kiam M. Tey, Kiyoshi Fukahori, Paul J. Hurst, Manprit Kapoor

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

Authors: John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

Authors: Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno

UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems

Authors: Yoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma, Daisuke Ohgarane, Satoru Saito, Koji Dairiki, Hidekazu Takahashi, Yutaka Shionoiri, Tomoaki Atsumi, Takeshi Osada, Kei Takahashi, Takanori Matsuzaki, Hiroyuki Takashina, Yoshinari Yamashita, Shunpei Yamazaki

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping

Authors: Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Authors: Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Authors: Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

Authors: Juergen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel

A Continuous-Grain Silicon-System LCD With Optical Input Function

Authors: Chris J. Brown, Hiromi Kato, Kazuhiro Maeda, Ben Hadwen

A 40-44 Gb/s 3 Oversampling CMOS CDR/1: 16 DEMUX

Authors: Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker

A 1/2.7-in 2.96 MPixel CMOS Image Sensor With Double CDS Architecture for Full High-Definition Camcorders

Authors: Hidekazu Takahashi, Tomoyuki Noda, Takashi Matsuda, Takanori Watanabe, Mahito Shinohara, Toshiaki Endo, Shunsuke Takimoto, Ryuichi Mishima, Shigeru Nishimura, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs

Authors: Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi

A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme

Authors: Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura

A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers

Authors: Masato Koutani, Hiroshi Kawamura, Shinji Toyoyama, Kunihiko Iizuka

Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs

Authors: Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

A 16-Mb Toggle MRAM With Burst Modes

Authors: Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara

Over-100-Gb/s 1: 2 Demultiplexer Based on InP HBT Technology

Authors: Yasuyuki Suzuki, Masayuki Mamada, Zin Yamazaki

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

Authors: Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker

A High-Power Low-Distortion GaAs HBT Power Amplifier for Mobile Terminals Used in Broadband Wireless Applications

Authors: Tohru Oka, Masatomo Hasegawa, Michitoshi Hirata, Yoshihisa Amano, Yoshiteru Ishimaru, Hiroshi Kawamura, Keiichi Sakuno

Correction to "A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation"

Authors: Atsushi Yoshizawa and Yannis P. Tsividis

A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture

Authors: Hideo Yamasaki and Tadashi Shibata

22-29 GHz Ultra-Wideband CMOS Pulse Generator for Short-Range Radar Applications

Authors: Ahmet nc, B. B. M. Wasanthamala Badalawa, Minoru Fujishima

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Authors: Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya

A UWB-IR Transmitter With Digitally Controlled Pulse Generator

Authors: Takayasu Norimatsu, Ryosuke Fujiwara, Masaru Kokubo, Masayuki Miyazaki, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura

A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V

Authors: Kazuya Yamamoto, Takao Moriwaki, Hiroyuki Otsuka, Nobuyuki Ogawa, Kosei Maemura, Teruyuki Shimura

Analytical Determination of MOSFET's High-Frequency Noise Parameters From NF50 Measurements and Its Application in RFIC Design

Authors: Saman Asgaran, M. Jamal Deen, Chih-Hung Chen, G. Ali Rezvani, Yasmin Kamali, Yukihiro Kiyota

A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation

Authors: Atsushi Yoshizawa and Yannis P. Tsividis

A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji Kawahito

A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques

Authors: Kazutaka Honda, Masanori Furuta, Shoji Kawahito

A 0.79-mm2 29-mW Real-Time Face Detection Core

Authors: Yuichi Hori and Tadahiro Kuroda

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor

Authors: Kunihiko Iizuka, Hiroshi Kawamura, Takanobu Fujiwara, Kanetomo Kagoshima, Shuichi Kawama, Hiroshi Kijima, Masato Koutani, Shinji Toyoyama, Keiichi Sakuno

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution

Authors: Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno

Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits

Authors: Stephen V. Kosonocky and Kazuo Yano

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-m CMOS

Authors: Afshin Momtaz, David Chung, Namik Kocaman, Jun Cao, Mario Caresosa, Bo Zhang, Ichiro Fujimori

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

Authors: Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Authors: Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

Authors: Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

MRAM Cell Technology for Over 500-MHz SoC

Authors: Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara

CMOS Smart Sensor for Monitoring the Quality of Perishables

Authors: Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-m InP HEMT Technology

Authors: Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-m CMOS

Authors: Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda

Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array

Authors: Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection

Authors: Toshihiko Yamasaki and Tadashi Shibata

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme

Authors: Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

Authors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

Authors: Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-m Technology

Authors: Hiroyuki Nakamoto, Daisuke Yamazaki, Takuji Yamamoto, Hajime Kurata, Satoshi Yamada, Kenji Mukaida, Tsuzumi Ninomiya, Takashi Ohkawa, Shoichi Masui, Kunihiko Gotoh

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture

Authors: Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu

An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display

Authors: Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

Authors: Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima

Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference

Authors: James D. Warnock, William Bidermann, Albert van der Werf, Katsuyuki Sato

A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling

Authors: Koichi Nose, Mikihiro Kajita, Masayuki Mizuno

A 375-mW Quadrature Bandpass$\Delta\Sigma$ADC With 8.5-MHz BW and 90-dB DR at 44 MHz

Authors: Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Donald Paterson, Steven Rose, Iuri Mehr, Qui Luu

A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change

Authors: Satoshi Yoshihara, Yoshikazu Nitta, Masaru Kikuchi, Ken Koseki, Yoshiharu Ito, Yoshiaki Inada, Souichiro Kuramochi, Hayato Wakabayashi, Masafumi Okano, Hiromi Kuriyama, Junichi Inutsuka, Akari Tajima, Tadashi Nakajima, Yoshiharu Kudoh, Fumihiko Koga, Yasuo Kasagi, Shinya Watanabe, Tetsuo Nomoto

A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

Authors: Mutsuo Daito, Hirofumi Matsui, Masaya Ueda, Kunihiko Iizuka

A New On-Chip Substrate-Coupled Inductor Model Implemented With Scalable Expressions

Authors: Ivan Chee Hong Lai and Minoru Fujishima

A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver

Authors: Tadashi Maeda, Noriaki Matsuno, Shinichi Hori, Tomoyuki Yamase, Takashi Tokairin, Kiyoshi Yanagisawa, Hitoshi Yano, Robert Walkington, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, Hikaru Hida

A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function

Authors: Taku Ogura, Masahiro Hosoda, Tomoya Ogawa, Tamiyu Kato, Akihiko Kanda, Tomoyuki Fujisawa, Satoshi Shimizu, Masafumi Katsumata

$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time

Authors: Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

A Burst-Mode Bit-Synchronization IC With Large Tolerance for Pulse-Width Distortion for Gigabit Ethernet PON

Authors: Hitoyuki Tagami, Seiji Kozaki, Kenichi Nakura, Shigeki Kohama, Masamichi Nogami, Kuniaki Motoshima

SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors

Authors: Masanao Yamaoka, Ryuta Tsuchiya, Takayuki Kawahara

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS

Authors: Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

Authors: Khurram Muhammad, Yo-Chuol Ho, Terry Mayhugh Jr., Chih-Ming Hung, Tom Jung, Imtinan Elahi, Charles Lin, Irene Yuanying Deng, Chan Fernando, John L. Wallberg, Sudheer K. Vemulapalli, Scott Larson, Thomas Murphy, Dirk Leipold, Patrick Cruise, J. Jaehnig, Meng-Chang Lee, Robert Bogdan Staszewski, Roman Staszewski, Ken Maggio

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

Authors: James D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jrgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

Authors: Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura

Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology

Authors: Satoshi Inaba, Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima, Yasunori Okayama, Takahiro Nakauchi, Kazunari Ishimaru, Hidemi Ishiuchi

Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications

Authors: Yasuhiko Sasaki, Naoki Kato, Hiroaki Nakaya

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

Authors: Nana Akahane, Shigetoshi Sugawa, Satoru Adachi, Kazuya Mori, Toshiyuki Ishiuchi, Koichi Mizobuchi

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

Authors: Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito

Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)

Authors: Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

Authors: Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

Authors: Hwa-Joon Oh, Silvia M. Mller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong

A low leakage SRAM macro with replica cell biasing scheme

Authors: Yasuhisa Takeyama, Hiroyuki Otake, Osamu Hirabayashi, Keiichi Kushida, Nobuaki Otsuka

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding

Authors: Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, Tadahiro Kuroda

A CMOS 1×-16× speed DVD write channel IC

Authors: Yoshiaki Konno, Koji Tomioka, Yusuke Aiba, Katsuhiko Yamazoe, Bang-Sup Song

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Authors: Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa'aki Tan'no, Takakuni Douseki

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique

Authors: Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara

Low-power InP-HEMT switch ICs integrating miniaturized 2×2 switches for 10-Gb/s systems

Authors: Hideki Kamitsuna, Yasuro Yamane, Masami Tokumitsu, Hirohiko Sugahara, Masahiro Muraguchi

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

Authors: Tadashi Maeda, Hitoshi Yano, Shinichi Hori, Noriaki Matsuno, Tomoyuki Yamase, Takashi Tokairin, Robert Walkington, Nobuhide Yoshida, Keiichi Numata, Kiyoshi Yanagisawa, Yuji Takahashi, Masahiro Fujii, Hikaru Hida

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM

Authors: Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara

The microarchitecture of the synergistic processor for a cell processor

Authors: Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Mller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

Authors: Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama

A 146-mm2 8-gb multi-level NAND flash memory with 70-nm CMOS technology

Authors: Takahiko Hara, Koichi Fukuda, Kazuhisa Kanazawa, Noboru Shibata, Koji Hosono, Hiroshi Maejima, Michio Nakagawa, Takumi Abe, Masatsugu Kojima, Masaki Fujiu, Yoshiaki Takeuchi, Kazumi Amemiya, Midori Morooka, Teruhiko Kamei, Hiroaki Nasu, Chi-Ming Wang, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Tohru Maruyama, Susumu Yoshikawa, Masaaki Higashitani, Tuan D. Pham, Yupin Fong, Toshiharu Watanabe

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

Authors: Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

Authors: Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

Authors: Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jrgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme

Authors: Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications

Authors: Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake

A 950-MHz rectifier circuit for sensor network tags with 10-m distance

Authors: Toshiyuki Umeda, Hiroshi Yoshida, Shuichi Sekine, Yumi Fujita, Takuji Suzuki, Shoji Otaka

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

Authors: Gil-Cho Ahn, Dong-Young Chang, Matthew E. Brown, Naoto Ozaki, Hiroshi Youra, Ken Yamamura, Koichi Hamashita, Kaoru Takasuka, Gbor C. Temes, Un-Ku Moon

Integrated stereo ΔΣ class D amplifier

Authors: Eric Gaalaas, Bill Yang Liu, Naoaki Nishimura, Robert Adams, Karl Sweetland

A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters

Authors: Mitsuhito Mase, Shoji Kawahito, Masaaki Sasaki, Yasuo Wakamori, Masanori Furuta

1.25-Gb/s burst-mode receiver ICs with quick response for PON systems

Authors: Makoto Nakamura, Yuki Imai, Yohtaro Umeda, Jun Endo, Yuji Akatsu

All-digital PLL and transmitter for mobile phones

Authors: Robert Bogdan Staszewski, John L. Wallberg, Sameh Rezeq, Chih-Ming Hung, Oren E. Eliezer, Sudheer K. Vemulapalli, Chan Fernando, Ken Maggio, Roman Staszewski, Nathen Barton, Meng-Chang Lee, Patrick Cruise, Mitch Entezari, Khurram Muhammad, Dirk Leipold

A high-speed CMOS image sensor with profile data acquiring function

Authors: Yukinobu Sugiyama, Munenori Takumi, Haruyoshi Toyoda, Naohisa Mukozaka, Atsushi Ihori, Takayuki Kurashina, Yosuke Nakamura, Takashi Tonbe, Seiichiro Mizuno

A 17-mW 0.66-mm2 direct-conversion receiver for 1-Mb/s cable replacement

Authors: Shwetabh Verma, Junfeng Xu, Mototsugu Hamada, Thomas H. Lee

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

Authors: Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto

A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor

Authors: Isao Takayanagi, Miho Shirakawa, Koji Mitani, Masayuki Sugawara, Steinar Iversen, Jrgen Moholt, Junichi Nakamura, Eric R. Fossum

Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

Authors: Yasushi Amamiya, Zin Yamazaki, Yasuyuki Suzuki, Masayuki Mamada, Hikaru Hida

A 90-GHz InP-HEMT lossy match amplifier with a 20-dB gain using a broadband matching technique

Authors: Yusuke Inoue, Masaru Sato, Toshihiro Ohki, Kozo Makiyama, Tsuyoshi Takahashi, Hisao Shigematsu, Tatsuya Hirose

C-band GaAs FET power amplifiers with 70-W output power and 50% PAE for satellite communication use

Authors: Akio Wakejima, Takahiro Asano, Takafumi Hirano, Masahiro Funabashi, Kohji Matsunaga

A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

Authors: Vishnu Balan, Joe Caroselli, Jenn-Gang Chern, Catherine Chow, Ratnakar Dadi, Chintan Desai, Leo Fang, David Hsu, Pankaj Joshi, Hiroshi Kimura, Cathy Ye Liu, Tzu-Wang Pan, Ryan Park, Cindy You, Yi Zeng, Eric Zhang, Freeman Zhong

A delta-sigma modulator for a 1-bit digital switching amplifier

Authors: Yoshihisa Fujimoto, Pascal Lo R, Masayuki Miyamoto

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

Authors: Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda

A 3-bit soft-decision IC for powerful forward error correction in 10-Gb/s optical communication systems

Authors: Hitoyuki Tagami, Tatsuya Kobayashi, Yoshikuni Miyata, Kazuhide Ouchi, Kazushige Sawada, Kazuo Kubo, Katsuhiko Kuno, Hideo Yoshida, Katsuhiro Shimizu, Takashi Mizuochi, Kuniaki Motoshima

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology

Authors: Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki

A delay-encoding-logic array processor for dynamic-programming matching of data sequences

Authors: Makoto Ogawa and Tadashi Shibata

An 800-MHz embedded DRAM with a concurrent refresh mode

Authors: Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer

A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique

Author: Kazuya Yamamoto

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

Authors: Masaki Sakakibara, Shoji Kawahito, Dwi Handoko, Nobuo Nakamura, Hiroki Satoh, Mizuho Higashi, Keiji Mabuchi, Hirofumi Sumi

A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with standard CMOS Process

Authors: Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi

A background optimization method for PLL by measuring phase jitter performance

Authors: Shiro Dosho, Naoshi Yanagisawa, Akira Matsuzawa

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

Authors: Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi

Introduction to the Special Issue

Authors: Bruce Gieseke and Tadahiro Kuroda

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router

Authors: Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization

Authors: Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

Authors: Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

Authors: Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda

A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits

Authors: Makoto Nagata, Takeshi Okumoto, Kazuo Taki

A 1.25-Gb/s CMOS burst-mode optical transceiver for ethernet PON system

Authors: Kazuko Nishimura, Hiroshi Kimura, Manabu Watanabe, Tetsuya Nagai, Kazuhiro Nojima, Kazumasa Gomyo, Masato Takata, Mitsuhiro Iwamoto, Hiroaki Asano

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS

Authors: Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda

A low-power and compact CDMA matched filter based on switched-current technology

Authors: Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

Authors: Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, Hubert Siedhoff

SiGe-HBT-based 54-gb/s 4: 1 multiplexer IC with full-rate clock for serial communication systems

Authors: Toru Masuda, Kenichi Ohhata, Nobuhiro Shiramizu, Eiji Ohue, Katsuya Oda, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Takashi Harada, Katsuyoshi Washio

A 6.7-fF/μm2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL

Authors: Makoto Takamiya and Masayuki Mizuno

A 44-μW 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range

Authors: Ken Yamamoto and Minoru Fujishima

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories

Authors: Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara

A 375 × 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique

Authors: Yusuke Oike, Makoto Ikeda, Kunihiro Asada

A nonvolatile programmable solid-electrolyte nanometer switch

Authors: Shunichi Kaeriyama, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, Masakazu Aono

Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin

Authors: Hiroshi Kawaguchi, Takao Someya, Tsuyoshi Sekitani, Takayasu Sakurai

Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS

Authors: Ken Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

Authors: Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

A design for a minimum Hamming-distance search using asynchronous digital techniques

Authors: Shigeru Nakahara and Takahiro Kawata

Dynamic voltage and frequency management for a low-power embedded microprocessor

Authors: Masakatsu Nakai, Satoshi Akui, Katsunori Seno, Tetsumasa Meguro, Takahiro Seki, Tetsuo Kondo, Akihiko Hashiguchi, Hirokazu Kawahara, Kazuo Kumano, Masayuki Shimura

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

Authors: Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jrgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

Mixed body bias techniques with fixed Vt and Ids generation circuits

Authors: Masaya Sumita, Shiro Sakiyama, Masayoshi Kinoshita, Yuta Araki, Yuichiro Ikeda, Kohei Fukuoka

A dual-core 64-bit ultraSPARC microprocessor for dense server applications

Authors: Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

Authors: Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi

A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure

Authors: Kunisato Yamaoka, Shunichi Iwanari, Yasuo Murakuki, Hiroshige Hirano, Masahiko Sakagami, Tetsuji Nakakuma, Takashi Miki, Yasushi Gohou

A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

Authors: Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada

1440 × 1080 pixel, 30 frames per second motion-JPEG 2000 codec for HD-movie transmission

Authors: Hideki Yamauchi, Shigeyuki Okada, Kazuhiko Taketa, Yuh Matsuda, Tsugio Mori, Tsuyoshi Watanabe, Yoshihiro Matsuo, Yoshifumi Matsushita

CMOS image sensors comprised of floating diffusion driving pixels with buried photodiode

Authors: Keiji Mabuchi, Nobuo Nakamura, Eiichi Funatsu, Takashi Abe, Tomoyuki Umeda, Tetsuro Hoshino, Ryoji Suzuki, Hirofumi Sumi

1/4-inch 2-mpixel MOS image sensor with 1.75 transistors/pixel

Authors: Mitsuyoshi Mori, Motonari Katsuno, Shigetaka Kasuga, Takahiko Murata, Takumi Yamaguchi

A +10-dBm IIP3 SiGe mixer with IM3 cancellation technique

Authors: Shoji Otaka, Mitsuyuki Ashida, Masato Ishii, Tetsuro Itakura

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

Authors: Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold, Chih-Ming Hung, Yo-Chuol Ho, John L. Wallberg, Chan Fernando, Ken Maggio, Roman Staszewski, Tom Jung, Jinseok Koh, Soji John, Irene Yuanying Deng, Vivek Sarda, Oscar Moreira-Tamayo, Valerian Mayega, Ran Katz, Ofer Friedman, Oren Eytan Eliezer, Elida de-Obaldia, Poras T. Balsara

120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs

Authors: Yasuyuki Suzuki, Zin Yamazaki, Yasushi Amamiya, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

A 3.9-μm pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel

Authors: Hidekazu Takahashi, Masakuni Kinoshita, Kazumichi Morita, Takahiro Shirai, Toshiaki Sato, Takayuki Kimura, Hiroshi Yuzurihara, Shunsuke Inoue, Shigeyuki Matsumoto

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)

Authors: Yadollah Eslami, Ali Sheikholeslami, Shoichi Masui, Toru Endo, Shoichiro Kawashima

Novel automatic tuning method of RC filters using a digital-DLL technique

Authors: Takashi Oshima, Kenji Maio, Willy Hioe, Yoshiyuki Shibahara

Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s

Authors: Hiroyuki Fukuyama, Kimikazu Sano, Koichi Murata, Hiroto Kitabayashi, Yasuro Yamane, Takatomo Enoki, Hirohiko Sugahara

A 80-gbit/s D-type flip-flop circuit using InP HEMT technology

Authors: Toshihide Suzuki, Tsuyoshi Takahashi, Tatsuya Hirose, Masahiko Takikawa

Development of 60-GHz front-end circuits for a high-data-rate communication system

Authors: Herbert Zirath, Toru Masuda, Rumen Kozhuharov, Mattias Ferndahl

A 1/3" VGA linear wide dynamic range CMOS image sensor implementing a predictive multiple sampling algorithm with overlapping integration intervals

Authors: Pablo M. Acosta-Serafini, Ichiro Masaki, Charles G. Sodini

Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain

Authors: Jin-Hyeok Choi, Yingxue Xu, Takayasu Sakurai

A sub-mW MPEG-4 motion estimation processor core for mobile video application

Authors: Masayuki Miyama, Junichi Miyakoshi, Yuki Kuroda, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

Authors: Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi

A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture

Authors: Yusuke Oike, Makoto Ikeda, Kunihiro Asada

Physical random number generator based on MOS structure after soft breakdown

Authors: Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita

A low-power switched-capacitor variable gain amplifier

Authors: Yoshihisa Fujimoto, Hitoshi Tani, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-μm CMOS transceiver for 802.11a/b/g wireless LAN

Authors: Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis, Nikos Haralabidis

90% write power-saving SRAM using sense-amplifying memory cell

Authors: Kouichi Kanda, Hattori Sadaaki, Takayasu Sakurai

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

Authors: Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

Authors: Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi

Wrapper-based bus implementation techniques for performance improvement and cost reduction

Authors: Kenichiro Anjo, Atsushi Okamura, Masato Motomura

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

Authors: Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect

Authors: Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara

A low-power microcontroller having a 0.5-μA standby current on-chip regulator with dual-reference scheme

Authors: Mitsuru Hiraki, Kenichi Fukui, Takayasu Ito

A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-μm CMOS

Authors: Takahide Kadoyama, Norihito Suzuki, Noboru Sasho, Hiroshi Iizuka, Ikuho Nagase, Hideaki Usukubo, Masayuki Katakura

A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking

Authors: Yoshio Miki, Tatsuya Saito, Hiroki Yamashita, Fumio Yuki, Takashige Baba, Akio Koyama, Masahito Sonehara

Introduction to the Special Issue

Authors: Yoshinobu Nakagome and Bruce Gieseke

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

Authors: Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade

21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs)

Authors: Takahiro Ohnakado, Satoshi Yamakawa, Takaaki Murakami, Akihiko Furukawa, Eiji Taniguchi, Hiro-omi Ueda, Noriharu Suematsu, Tatsuo Oomori

Design and implementation of real-time 3-D image sensor with 640 × 480 pixel resolution

Authors: Yusuke Oike, Makoto Ikeda, Kunihiro Asada

Post-fabrication clock-timing adjustment using genetic algorithms

Authors: Eiichi Takahashi, Yuji Kasai, Masahiro Murakawa, Tetsuya Higuchi

Macromodels in the frequency domain analysis of microwave resonators

Authors: Mamoru Ugajin, Akihiro Yamagishi, Junichi Kodate, Mitsuru Harada, Tsuneo Tsukahara

A shared-well dual-supply-voltage 64-bit ALU

Authors: Yasuhisa Shimazaki, Radu Zlatanovici, Borivoje Nikolic

0.18-μm CMOS Bluetooth analog receiver with -88-dBm sensitivity

Authors: Willy Hioe, Kenji Maio, Takashi Oshima, Yoshiyuki Shibahara, Takeshi Doi, Kiyoharu Ozaki, Satoshi Arayashiki

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

Authors: Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara

A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory

Authors: Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu

A dynamically reconfigurable SIMD processor for a vision chip

Authors: Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

Authors: Koichi Murata, Kimikazu Sano, Hiroto Kitabayashi, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki

A 120×110 position sensor with the capability of sensitive and selective light detection in wide dynamic range for robust active range finding

Authors: Yusuke Oike, Makoto Ikeda, Kunihiro Asada

A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling

Authors: Lalitkumar Nathawad, Ryohei Urata, Bruce A. Wooley, David A. B. Miller

A CMOS multichannel 10-Gb/s transceiver

Authors: Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN

Authors: Iason Vassiliou, Kostis Vavelidis, Theodore Georgantas, Sofoklis Plevridis, Nikos Haralabidis, George Kamoulakos, Charalambos Kapnistis, Spyros Kavadias, Yiannis Kokolakis, Panagiotis Merakos, Jacques C. Rudell, Akira Yamanaka, Stamatis Bouras, Ilias Bouras

A 1.3-GHz fifth-generation SPARC64 microprocessor

Authors: Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama

A single-chip 802.11a MAC/PHY with a 32-b RISC processor

Authors: Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, Yasuo Unekawa

A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements

Authors: Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda

A 400-MT/s 6.4-GB/s multiprocessor bus interface

Authors: Harry Muljono, Beom-Taek Lee, Yanmei (Kathy) Tian, Yanbin (Eddie) Wang, Mubeen Atha, Tiffany Huang, Mitsuhiro Adachi, Stefan Rusu

A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications

Authors: Koji Okamoto, Takashi Morie, Akira Yamamoto, Kouichi Nagano, Koji Sushihara, Hiroyuki Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, Toru Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, Tadashi Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, Akira Matsuzawa

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

Authors: Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi

A 32-Mb chain FeRAM with segment/stitch array architecture

Authors: Shinichiro Shiratake, Tadashi Miyakawa, Yoshiaki Takeuchi, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Kohei Oikawa, Tohru Ozaki, Iwao Kunishima, Koji Yamakawa, Shigeki Sugimoto, Daisaburo Takashima, Hans-Oliver Joachim, Norbert Rehm, Joerg Wohlfahrt, Nicolas Nagel, Gerhard Beitel, Michael Jacob, Thomas Roehr

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

Authors: Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto

Pipelined delay-sum architecture based on bucket-brigade devices for on-chip ultrasound beamforming

Authors: Yaowu Mo, Tsunehisa Tanaka, Shigeru Arita, Akira Tsuchitani, Koji Inoue, Yoshihiko Suzuki

A four-input beam-forming downconverter for adaptive antennas

Authors: Takafumi Yamaji, Daisuke Kurose, Osamu Watanabe, Shuichi Obayashi, Tetsuro Itakura

An over-110-GHz InP HEMT flip-chip distributed baseband amplifier with inverted microstrip line structure for optical transmission system

Authors: Satoshi Masuda, Tsuyoshi Takahashi, Kazukiyo Joshin

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

Authors: Kimikazu Sano, Koichi Murata, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki

Demodulators for a zero-IF Bluetooth receiver

Authors: Sohrab Samadian, Ryoji Hayashi, Asad A. Abidi

A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications

Authors: Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano

A 256256 compact CMOS image sensor with on-chip motion detection function

Authors: Seiichiro Mizuno, Kazuki Fujita, Hiroo Yamamoto, Naohisa Mukozaka, Haruyoshi Toyoda

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

Authors: Hirobumi Watanabe, Shunsuke Ando, Hideyuki Aota, Masanori Dainin, Yong-Jin Chun, Kenji Taniguchi

Guest Editorial

Authors: Shekhar Borkar and Yoshinobu Nakagome

A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture

Authors: Masanori Fujibayashi, Toshiyuki Nozawa, Takahiro Nakayama, Kenji Mochizuki, Masahiro Konda, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi

A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications

Authors: Hiroshi Komurasaki, Tomohiro Sano, Tetsuya Heima, Kazuya Yamamoto, Hideyuki Wakada, Ikuo Yasui, Masayoshi Ono, Toshitsugu Miwa, Hisayasu Sato, Takahiro Miki, Naoyuki Kato

A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer

Authors: Yoshiharu Kudoh, Muneo Fukaishi, Masayuki Mizuno

A ferroelectric memory-based secure dynamically programmable gate array

Authors: Shoichi Masui, Tsuzumi Ninomiya, Michiya Oura, Wataru Yokozeki, Kenji Mukaida, Shoichiro Kawashima

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

Authors: Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama

Threshold-voltage balance for minimum supply operation [LV CMOS chips]

Authors: Goichi Ono and Masayuki Miyazaki

Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology

Authors: Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano

A single-chip MPEG-2 codec based on customizable media embedded processor

Authors: Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui

A 402-output TFT-LCD driver IC with power control based on the number of colors selected

Authors: Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda

An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions

Authors: Masahiro Murakawa, Toshio Adachi, Yoshihiro Niino, Yuji Kasai, Eiichi Takahashi, Kaoru Takasuka, Tetsuya Higuchi

A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories

Authors: Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima

A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology

Authors: Tsuneaki Fuse, Masako Ohta, Motoki Tokumasu, Hiroshige Fujii, Shigeru Kawanaka, Atsushi Kameyama

A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method

Authors: Ryuichi Hashido, Akihiro Suzuki, Akihiko Iwata, Tatsuki Okamoto, Yukio Satoh, Mitsuo Inoue

A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture

Authors: Daisuke Miyazaki, Shoji Kawahito, Masanori Furuta

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

Authors: Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

Authors: Takamoto Watanabe and Shigenori Yamauchi

A signal-processing CMOS image sensor using a simple analog operation

Authors: Yoshinori Muramatsu, Susumu Kurosawa, Masayuki Furumiya, Hiroaki Ohkubo, Yasutaka Nakashiba

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

Authors: Akira Tanabe, Yasushi Nakahara, Akio Furukawa, Tohru Mogami

An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering

Authors: Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino

DC-coupled IF stage design for a 900-MHz ISM receiver

Authors: Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino

A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology

Authors: Takamoto Watanabe, Tamotsu Mizuno, Yasuaki Makino

OC-192 transmitter and receiver in standard 0.18-μm CMOS

Authors: Jun Cao, Michael M. Green, Afshin Momtaz, Kambiz Vakilian, David Chung, Keh-Chee Jen, Mario Caresosa, Xin Wang, Wee-Guan Tan, Yijun Cai, Ichiro Fujimori, Armond Hairapetian

A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology

Authors: Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe

A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications

Authors: Takashi Hashimoto, Masahiro Ohashi, Masatoshi Matsuo, Shun-ichi Kuromaru, Toshihiro Mori-iwa, Mana Hamada, Yuji Sugisawa, Hiroto Tomita, Masashi Hoshino, Tsuyoshi Nakamura, Ken-ichi Ishida, Kazuhiro Watada, Taro Fukunaga, Junji Michiyama

A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed

Authors: Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che

A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture

Authors: James T. Kao, Masayuki Miyazaki, Anantha P. Chandrakasan

A quasi-matrix ferroelectric memory for future silicon storage

Authors: Toshiyuki Nishihara and Yasuyuki Ito

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

Authors: Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns

Memory design using a one-transistor gain cell on SOI

Authors: Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

Authors: Toru Tanzawa, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba, Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, Shigeru Atsumi

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs

Authors: Hiroki Morimura, Satoshi Shigematsu, Toshishige Shimamura, Katsuyuki Machida, Hakaru Kyuragi

High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories

Authors: Toru Tanzawa, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi

Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors

Authors: Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki

A 54-GHz distributed amplifier with 6-VPP output for a 40-Gb/s LiNbO3 modulator driver

Authors: Hisao Shigematsu, Masaru Sato, Tatsuya Hirose, Yuu Watanabe

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers

Authors: Junichi Yamada, Tohru Miwa, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Hidemitsu Mori, Seiichi Takahashi, Hidenori Takeuchi, Takemitsu Kunio

A 7-GHz 1.8-dB NF CMOS low-noise amplifier

Authors: Ryuichi Fujimoto, Kenji Kojima, Shoji Otaka

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability

Authors: Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka

A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching

Authors: Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura

Novel cell-AGC technique for burst-mode CMOS preamplifier with wide dynamic range and high sensitivity for ATM-PON system

Authors: Shinji Yamashita, Satoshi Ide, Kazuyuki Mori, Atsushi Hayakawa, Norio Ueno, Kazuhiro Tanaka

High-frequency characterization of on-chip digital interconnects

Authors: Bendik Kleveland, Xiaoning Qi, Liam Madden, Takeshi Furusawa, Robert W. Dutton, Mark A. Horowitz, S. Simon Wong

A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell

Authors: Nobutaro Shibata, Mayumi Watanabe, Yasuyuki Tanabe

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process

Authors: Shiro Dosho, Takashi Morie, Hirokuni Fujiyama

A 63-μW standby power microcontroller with on-chip hybrid regulator scheme

Authors: Mitsuru Hiraki, Takayasu Ito, Atsushi Fujiwara, Taichi Ohashi, Tetsuro Hamano, Takaaki Noda

Bitline GND sensing technique for low-voltage operation FeRAM

Authors: Shoichiro Kawashima, Toru Endo, Akira Yamamoto, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Keizo Morita, Masaki Aoki

A cell transistor scalable DRAM array architecture

Authors: Daisaburo Takashima and Hiroaki Nakano

A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range

Authors: Takafumi Yamaji, Nobuo Kanou, Tetsuro Itakura

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

Authors: Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi

Guest editorial

Authors: Masakazu Yamashina and Shekhar Y. Borkar

A low-impedance open-bitline array for multigigabit DRAM

Authors: Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura

Fully integrated CMOS power amplifier design using the distributed active-transformer architecture

Authors: Ichiro Aoki, Scott D. Kee, David B. Rutledge, Ali Hajimiri

Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation

Authors: Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz

A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system

Authors: Satoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuya Matsumura

VTH-hopping scheme to reduce subthreshold leakage for low-power processors

Authors: Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai

A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier

Authors: Troy Stockstad and Hirokazu Yoshizawa

A 40-μA/channel compensated 18-channel strain gauge measurement system for stress monitoring in dental implants

Authors: Troy Stockstad and Hirokazu Yoshizawa

Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers

Authors: Atsushi Yoshizawa and Yannis P. Tsividis

Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance

Authors: Hans Jrgen Mattausch, Takayuki Gyohten, Yoshihiro Soda, Tetsushi Koide

A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias

Authors: Masayuki Miyazaki, Goichi Ono, Koichiro Ishibashi

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

Authors: Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino

Circuit techniques for a 1.8-V-only NAND flash memory

Authors: Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura

A fully integrated SONET OC-48 transceiver in standard CMOS

Authors: Afshin Momtaz, Jun Cao, Mario Caresosa, Armond Hairapetian, David Chung, Kambiz Vakilian, Michael M. Green, Wee-Guan Tan, Keh-Chee Jen, Ichiro Fujimori, Yijun Cai

An analog front-end chip set employing an electro-optical mixed design on SPICE for 5-Gb/s/ch parallel optical interconnection

Authors: Takeshi Nagahori, Kazunori Miyoshi, Yukio Aizawa, Yuki Kusachi, Yasuaki Nukada, Nobuharu Kami, Naofumi Suzuki

A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers

Authors: Jeffrey A. Weldon, R. Sekhar Narayanaswami, Jacques Christophe Rudell, Li Lin, Masanori Otsuka, Sbastien Dedieu, Luns Tee, King-Chun Tsai, Cheol-Woong Lee, Paul R. Gray

A 126.6-mm2 AND-type 512-Mb flash memory with 1.8-V power supply

Authors: Tatsuya Ishii, Kazuyoshi Oshima, Hiroshi Sato, Satoshi Noda, Jiro Kishimoto, Hiroaki Kotani, Atsushi Nozoe, Kazunori Furusawa, Takayuki Yoshitake, Masataka Kato, Masahito Takahashi, Akihiko Sato, Shoji Kubono, Kiichi Manita, Kenji Koda, Takeshi Nakayama, Akira Hosogane

A 150-MHz graphics rendering processor with 256-Mb embedded DRAM

Authors: Aurangzeb K. Khan, Hidetaka Magoshi, Tadashi Matsumoto, Jun-Ichi Fujita, Makoto Furuhashi, Masatoshi Imai, Yoshikazu Kurose, Morio Sato, Katsuhiko Sato, Yujiro Yamashita, Kinying Kwan, Duc-Ngoc Le, John H. Yu, Trung Nguyen, Steven Yang, Allen Tsou, King Chow, John Shen, Min Li, Jun Li, Hong Zhao, Kenji Yoshida

A 250-MHz single-chip multiprocessor for audio and video signal processing

Authors: Tatsuya Koyama, Keisuke Inoue, Hirokazu Hanaki, Masahiro Yasue, Eiji Iwata

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Authors: Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse

Authors: Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

A 76-mm2 8-Mb chain ferroelectric memory

Authors: Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications

Authors: Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi

A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture

Authors: Kouichi Yamaguchi, Muneo Fukaishi, Takehiko Sakamoto, Naoto Akiyama, Kazuyuki Nakamura

A mixed-signal 0.18-μm CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM

Authors: Takashi Yamamoto, Shin-Ichi Gotoh, Toshihiko Takahashi, Kozo Irie, Kazuya Ohshima, Nobuhiro Mimura, Kazutoshi Aida, Toshinori Maeda, Koji Sushihara, Yoichi Okamoto, Yasuhiro Tai, Makoto Usui, Takeshi Nakajima, Takahiro Ochi, Katsuhiko Komichi, Akira Matsuzawa

Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs

Authors: Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai

Accurate in situ measurement of peak noise and delay change induced by interconnect coupling

Authors: Takashi Sato, Dennis Sylvester, Yu Cao, Chenming Hu

A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs

Authors: Nobutaro Shibata, Mayumi Watanabe, Yasuhiro Sato, Takako Ishihara, Yukio Komine

An auto-gain control transimpedance amplifier with low noise and wide input dynamic range for 10-Gb/s optical communication systems

Authors: Hitoshi Ikeda, Tomoyuki Ohshima, Masanori Tsunotani, Toshihiko Ichioka, Tamotsu Kimura

Three-dimensional MMIC technology for low-cost millimeter-wave MMICs

Authors: Kenjiro Nishikawa, Kenji Kamogawa, Belinda Piernas, Masami Tokumitsu, Suehiro Sugitani, Ichihiko Toyoda, Katsuhiko Araki

A 49-GHz preamplifier with a transimpedance gain of 52 dBΩ using InP HEMTs

Authors: Hisao Shigematsu, Masaru Sato, Toshihide Suzuki, Tsuyoshi Takahashi, Kenji Imanishi, Naoki Hara, Hiroaki Ohnishi, Yuu Watanaba

Adaptive analog IF signal processor for a wide-band CMOS wireless receiver

Authors: Farbod Behbahani, Ali Karimi-Sanjaani, Wee-Guan Tan, Andreas Roithmeier, John C. Leete, Koichi Hoshino, Asad A. Abidi

A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution

Authors: Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata

A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique

Authors: Hideyuki Nosaka, Yo Yamaguchi, Akihiro Yamagishi, Hiroyuki Fukuyama, Masahiro Muraguchi

100-Mbit/s single-chip Q-VLMS MLSE equalizer LSI for TDMA mobile radio communications

Authors: Yushi Shirato, Kiyoshi Kobayashi, Satoshi Denno

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

Authors: Kazuya Yamamoto, Tetsuya Heima, Akihiko Furukawa, Masayoshi Ono, Yasushi Hashizume, Hiroshi Komurasaki, Shigenobu Maeda, Hisayasu Sato, Naoyuki Kato

A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs

Authors: Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya

CMOS mixers and polyphase filters for large image rejection

Authors: Farbod Behbahani, Yoji Kishigami, John C. Leete, Asad A. Abidi

A design for high-speed low-power CMOS fully parallel content-addressable memory macros

Authors: Hisatada Miyatake, Masahiro Tanaka, Yotaro Mori

0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation

Authors: Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka

A bitline leakage compensation scheme for low-voltage SRAMs

Authors: Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda

True color 1024×768 microdisplay with analog in-pixel pulsewidth modulation and retinal averaging offset correction

Authors: Travis N. Blalock, Neela B. Gaddis, Ken A. Nishimura, Thomas A. Knotts

Guest editorial

Authors: David B. Scott and Masakazu Yamashina

A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories

Authors: Ken Takeuchi and Tomoharu Tanaka

A computational image sensor with adaptive pixel-based integration time

Authors: Takayuki Hamamoto and Kiyoharu Aizawa

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s

Author: Yasuhiro Sugimoto

CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops

Authors: Kunihiko Iizuka, Masayuki Miyamoto, Yoshiji Ohta, Takahiro Suyama, Keita Hara, Shuichi Kawama, Hirofumi Matsui, Shin'ichiro Azuma, Shigenari Taguchi, Yoshihisa Fujimoto, Daniel Senderowicz

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

Authors: Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio

Physical design guides for substrate noise reduction in CMOS digital circuits

Authors: Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield

Authors: Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%

Authors: Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba

A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree

Authors: Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba

An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode

Authors: Kimikazu Sano, Koichi Murata, Taiichi Otsuji, Tomoyuki Akeyoshi, Naofumi Shimizu, Eiichi Sano

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current

Authors: Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka

An image-rejecting mixer and vector filter with 55-dB image rejection over process, temperature, and transistor mismatch

Authors: Thomas Hornak, Knud L. Knudsen, Andrew Z. Grzegorek, Ken A. Nishimura, William J. McFarland

Wordline voltage generating system for low-power low-voltage flash memories

Authors: Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi

Design methodology of embedded DRAM with virtual-socket architecture

Authors: Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara

A 2.4-GHz low-IF receiver for wideband WLAN in 6-μm CMOS-architecture and front-end

Authors: Farbod Behbahani, John C. Leete, Yoji Kishigami, Andreas Roithmeier, Koichi Hoshino, Asad A. Abidi

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio

Authors: Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama, Steve Kosic, Jun Cao, Shu-Lap Chan

2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V

Authors: Mitsuru Harada, Tsuneo Tsukahara, Junichi Kodate, Akihiro Yamagishi, Junzo Yamada

A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI

Authors: Kenji Kawai and Haruhiko Ichino

A low-power low-noise accurate linear-in-dB variable-gain amplifier with 500-MHz bandwidth

Authors: Shoji Otaka, Gaku Takemura, Hiroshi Tanimoto

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR

Authors: Hui Pan, Masahiro Segami, Michael Choi, Jing Cao, Asad A. Abidi

A 2-V CMOS cellular transceiver front-end

Authors: Michel S. J. Steyaert, Johan Janssens, Bram De Muer, Marc Borremans, Nobuyuki Itoh

A progressive scan CCD image sensor for DSC applications

Authors: Tetsuo Yamada, Katsumi Ikeda, Yong-Gwan Kim, Hideki Wakoh, Tetsuo Toma, Tomohiro Sakamoto, Kazuaki Ogawa, Eiichi Okamoto, Kazuyuki Masukane, Kazuya Oda, Masafumi Inuiya

A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode

Authors: Kazuya Yonemoto and Hirofumi Sumi

An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2/RAM)

Authors: Yasuhiro Agata, Kenji Motomochi, Yoshifumi Fukushima, Masanori Shirahama, Marefusa Kurumada, Naoki Kuroda, Hiroyuki Sadakata, Kohtaro Hayashi, Toshio Yamada, Kazunari Takahashi, Tsutomu Fujita

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

Authors: Shigeru Atsumi, Akira Umezawa, Tooru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe

A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays

Authors: Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi

A third-generation SPARC V9 64-b microprocessor

Authors: Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

Authors: Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara

A parallel vector-quantization processor eliminating redundant calculations for real-time motion picture compression

Authors: Toshiyuki Nozawa, Masahiro Konda, Masanori Fujibayashi, Makoto Imai, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi

A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"

Authors: Takanori Saeki, Masafumi Mitsuishi, Hiroaki Iwaki, Mitsuaki Tagishi

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

Authors: Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

Authors: Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

Authors: Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current

Authors: Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai

1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs

Authors: Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada

Design of a sense circuit for low-voltage flash memories

Authors: Toru Tanzawa, Yoshinori Takano, Tadayuki Taura, Shigeru Atsumi

A CW 4-W Ka-band power amplifier utilizing MMIC multichip technology

Authors: Kohji Matsunaga, Ikuo Miura, Naotaka Iwata

A 1.9-GHz CMOS VCO with micromachined electromechanically tunable capacitors

Authors: Aleksander Dec and Ken Suyama

A multibit delta-sigma audio DAC with 120-dB dynamic range

Authors: Ichiro Fujimori, Akihiko Nogi, Tetsuro Sugimoto

A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs

Authors: Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM

Authors: Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

Authors: Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani

A 3.2-V operation single-chip dual-band AlGaAs/GaAs HBT MMIC power amplifier with active feedback circuit technique

Authors: Kazuya Yamamoto, Satoshi Suzuki, Kazutomi Mori, Tomoyuki Asada, Toshio Okuda, Akira Inoue, Takeshi Miura, Kenichiro Chomei, Ryo Hattori, Masahide Yamanouchi, Teruyuki Shimura

High-performance embedded SOI DRAM architecture for the low-power supply

Authors: Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing

Authors: Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki

14-bit 2.2-MS/s sigma-delta ADC's

Authors: James C. Morizio, Michael Hoke, Taskin Koak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, Masao Nakaya

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

Authors: Yun-Nan Chang, Hiroshi Suzuki, Keshab K. Parhi

A design for high noise rejection in a pseudodifferential preamplifier for hard disk drives

Authors: Indumini Ranmuthu, Paul M. Emerson, Ken Maggio, Hong Jiang, Ashish Manjekar, Bryan E. Bloodworth, Mark Guastaferro

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

Authors: Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman

A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors

Authors: Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

Authors: Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

Authors: Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata

A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming

Authors: Hiromi Nobukata, Shunsuke Takagi, Keizo Hiraga, Takeshi Ohgishi, Masaru Miyashita, Kazuto Kamimura, Shinji Hiramatsu, Kiyohisa Sakai, Takahiro Ishida, Hideki Arakawa, Masahiko Itoh, Ihachi Naiki, Masanori Noda

Guest editorial

Authors: Masao Taguchi and David B. Scott

A source-line programming scheme for low-voltage operation NAND flash memories

Authors: Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui

A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing

Authors: Takeshi Ikenaga and Takeshi Ogura

Low-power CMOS digital design with dual embedded adaptive power supplies

Authors: Tadahiro Kuroda and Mototsugu Hamada

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor

Authors: Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz

Authors: Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta

A distributed selector IC using GaAs MESFET's with multilayer-interconnection structure

Authors: Koichi Murata, Taiichi Otsuji, Yuhki Imai, Suehiro Sugitani

A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection

Authors: Eduard Sckinger, Yusuke Ota, Thaddeus J. Gabara, Wilhelm C. Fischer

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions

Authors: Takeshi Suzuki, Keiichi Higeta, Yasuhiro Fujimura, Kazumasa Ando, Hiroaki Nambu, Ryo Yamagata, Atsuo Hotta, Kunihiko Yamaguchi

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Authors: Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda

A multigigahertz Josephson-semiconductor interface circuit using 77-K differential monolithic HEMT amplifier and 4.2-K JJ high-voltage driver for superconductor-semiconductor electronic hybrid systems

Authors: Naoki Harada, Akira Watanabe, Yuji Awano, Kohki Hikosaka, Naoki Yokoyama

A 1/2-in, 1.3 M-pixel progressive-scan CCD image sensor employing 0.25-μm gap single-layer poly-Si electrodes

Authors: Masayuki Furumiya, Keisuke Hatano, Yasutaka Nakashiba, Ichiro Murakami, Tohru Yamada, Takashi Nakano, Yukiya Kawakami, Toru Kawasaki, Yasuaki Hokari

A 2D CMOS microfluxgate sensor system for digital detection of weak magnetic fields

Authors: Masayuki Furumiya, Keisuke Hatano, Yasutaka Nakashiba, Ichiro Murakami, Tohru Yamada, Takashi Nakano, Yukiya Kawakami, Toru Kawasaki, Yasuaki Hokari

A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration

Authors: Eiji Oki, Naoaki Yamanaka, Yusuke Ohtomo, Kazuhiko Okazaki, Ryusuke Kawano

A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection

Authors: Eduard Sckinger, Yusuke Ota, Thaddeus J. Gabara, Wilhelm C. Fischer

A single-chip fingerprint sensor and identifier

Authors: Satoshi Shigematsu, Hiroki Morimura, Yasuyuki Tanabe, Takuya Adachi, Katsuyuki Machida

An accurate center frequency tuning scheme for 450-KHz CMOS Gm-C bandpass filters

Authors: Hiroshi Yamazaki, Kazuaki Oishi, Kunihiko Gotoh

A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology

Authors: Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui

A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

Authors: Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism

Authors: Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada

A 29-mm2, 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump

Authors: Yoshikazu Miyawaki, Osamu Ishizaki, Yoshihiko Okihara, Tsutomu Inaba, Fumihiko Nitta, Masaaki Mihara, Takashi Hayasaka, Kazuo Kobayashi, Tadashi Omae, Hiroshi Kimura, Satoshi Shimizu, Hiromi Makimoto, Yoshiki Kawajiri, Masashi Wada, Hirofumi Sonoyama, Jun Etoh

An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

Authors: Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications

Authors: Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi

A 500-MHz pipelined burst SRAM with improved SER immunity

Authors: Hirotoshi Sato, Tomohisa Wada, Shigeki Ohbayashi, Kunihiko Kozaru, Yasuyuki Okamoto, Yoshiko Higashide, Tadayuki Shimizu, Yukio Maki, Rui Morimoto, Hisakazu Otoi, Tsuyoshi Koga, Hiroki Honda, Makoto Taniguchi, Yutaka Arita, Toru Shiomi

A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder

Authors: Masakazu Suzuoki, Ken Kutaragi, Toshiyuki Hiroi, Hidetaka Magoshi, Shin'ichi Okamoto, Masaaki Oka, Akio Ohba, Yasuyuki Yamamoto, Makoto Furuhashi, Masayoshi Tanaka, Teiji Yutaka, Toyoshi Okada, Masato Nagamatsu, Yukihiro Urakawa, Masami Funyu, Atsushi Kunimatsu, Harutaka Goto, Kazuhiro Hashimoto, Nobuhiro Ide, Hiroaki Murakami, Yukio Ohtaguro, Akira Aono

110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock

Authors: Toshiro Takahashi, Takashi Muto, Yuji Shirai, Fumihiko Shirotori, Yoshifumi Takada, Akira Yamagiwa, Akira Nishida, Atsuo Hotta, Tadashi Kiyuna

A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme

Authors: Satoru Takase and Natsuki Kushiyama

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive

Authors: Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka

Noncomplimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAM

Authors: Satoshi Utsugi, Masami Hanyu, Yoshinori Muramatsu, Tadahiko Sugibayashi

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications

Authors: Muneo Fukaishi, Satoshi Nakamura, Akio Tajima, Yasushi Kinoshita, Yoshihiko Suemura, Hisamitsu Suzuki, Toshiro Itani, Hidenobu Miyamoto, Naoya Henmi, Tohru Yamazaki, Michio Yotsuyanagi

A 5-GHz frequency-doubling quadrature modulator with a ring-type local oscillator

Authors: Hiroto Matsuoka and Tsuneo Tsukahara

40-Gbit/s TDM transmission technologies based on ultra-high-speed ICs

Authors: Yutaka Miyamoto, Mikio Yoneyama, Taiichi Otsuji, Kazushige Yonenaga, Naofumi Shimizu

Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamic range implemented in SiGe HBT

Authors: Kenichi Ohhata, Toru Masuda, Eiji Ohue, Katsuyoshi Washio

L/S-band 140-W push-pull power AlGaAs/GaAs HFET's for digital cellular base stations

Authors: Isao Takenaka, Kouji Ishikura, Hidemasa Takahashi, Kazunori Asano, Junko Morikawa, K. Satou, K. Kishi, Kouichi Hasegawa, K. Tokunaga, Fumiaki Emori, Masaaki Kuzuhara

A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC

Authors: Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu

Low-insertion-loss DP3T MMIC switch for dual-band cellular phones

Authors: Akira Nagayama, Masatoyo Nishibe, Takayuki Inaoka, Nobuhiro Mineshima

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

Authors: Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura

Optimization of word-line booster circuits for low-voltage flash memories

Authors: Toru Tanzawa and Shigeru Atsumi

A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor

Authors: Atsushi Mohri, Akira Yamada, Y. Yoshida, Hisakazu Sato, Hidehiro Takata, K. Nakakimura, M. Hashizume, Y. Shimotsuma, K. Tsuchihashi

A 2000-MOPS embedded RISC processor with a Rambus DRAM controller

Authors: Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs

Authors: Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino

A fully parallel vector-quantization processor for real-time motion-picture compression

Authors: Akira Nakada, Tadashi Shibata, Masahiro Konda, Tatsuo Morimoto, Tadahiro Ohmi

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers

Authors: Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe

MOSFET-only switched-capacitor circuits in digital CMOS technology

Authors: Hirokazu Yoshizawa, Yunteng Huang, Paul F. Ferguson Jr., Gabor C. Temes

A CMOS bandgap reference circuit with sub-1-V operation

Authors: Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, Koji Sakui

Guest Editorial

Authors: William Bidermann and Masao Taguchi

High-speed DRAM architecture development

Authors: Hiroaki Ikeda and Hidemori Inukai

A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM

Authors: Takashi Sato, Yoji Nishio, Toshio Sugano, Yoshinobu Nakagome

A 1-GHz logic circuit family with sense amplifiers

Authors: Osamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong

A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories

Authors: Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui

A 5.3-GB/s embedded SDRAM core with slight-boost scheme

Authors: Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada

New three-dimensional memory array architecture for future ultrahigh-density DRAM

Authors: Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface

Authors: Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada

A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver for wireless applications

Authors: Kazuya Yamamoto, Takao Moriwaki, Takayuki Fujii, Jun Otsuji, Miyo Miyashita, Yukio Miyazaki, Kazuo Nishitani

CMOS technology-year 2010 and beyond

Author: Hiroshi Iwai

A direct-skew-detect synchronous mirror delay for application-specific integrated circuits

Authors: Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, Hisamitsu Suzuki

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design

Authors: Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

Authors: Nick Lindert, Toshihiro Sugii, Stephen Tang, Chenming Hu

A 5-GHz-band multifunctional BiCMOS transceiver chip for GMSK modulation wireless systems

Authors: Mohammad Madihian, Tomislav Drenski, Laurent Desclos, Hiroshi Yoshida, Hiroshi Hirabayashi, Tohru Yamazaki

A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links

Authors: Kenichi Ohhata, Toru Masuda, Kazuo Imai, Ryoji Takeyari, Katsuyoshi Washio

A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure

Authors: Akira Ohta, Norio Higashisaka, Tetsuya Heima, Takayuki Hisaka, Hirofumi Nakano, Ryuji Ohmura, Tadashi Takagi, Noriyuki Tanino

A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter

Authors: Ichiro Fujimori and Tetsuro Sugimoto

A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture

Authors: Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi

A 16-μA interface circuit for a capacitive flow sensor

Authors: Bertram Rodgers, Sofjan Goenawan, Mohammad Yunus, Yoshikazu Kaneko, Junichi Yoshiike

A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier

Authors: Akira Tanabe, Masaaki Soda, Yasushi Nakahara, Takao Tamura, Kazuyoshi Yoshida, Akio Furukawa

A CMOS 6-b, 400-MSample/s ADC with error correction

Authors: Sanroku Tsukamoto, William G. Schofield, Toshiaki Endo

An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter

Authors: Takafumi Yamaji, Hiroshi Tanimoto, Hideyuki Kokatsu

A third-order ΔΣ modulator using second-order noise-shaping dynamic element matching

Authors: Akira Yasuda, Hiroshi Tanimoto, Tetsuya Iida

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line

Authors: Satoshi Eto, Masato Matsumiya, Masato Takita, Yuki Ishii, Toshikazu Nakamura, Kuninori Kawabata, Hideki Kano, Ayako Kitamoto, Toshimi Ikeda, Toru Koga, Mitsuhiro Higashiho, Yuji Serizawa, Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Masao Taguchi

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency

Authors: Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino

An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing

Authors: Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura, Masakazu Yamashina

A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

Authors: Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications

Authors: Hajime Kubosawa, Hiromasa Takahashi, Satoshi Ando, Yoshimi Asada, Akira Asato, Atsuhiro Suga, Michihide Kimura, Naoshi Higaki, Hideo Miyake, Tomio Sato, Hideaki Anbutsu, Toshitaka Tsuda, Tetsuo Yoshimura, Isao Amano, Mutsuaki Kai, Shin Mitarai

Low-power SRAM design using half-swing pulse-mode techniques

Authors: Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, Isao Fukushi, Tetsuo Izawa, Shin Mitarai

A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter

Authors: Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

Authors: Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Yasuhiro Fujimura, Kazumasa Ando, Takeshi Kusunoki, Kunihiko Yamaguchi, Noriyuki Homma

A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H±288, V: ±96) motion estimation and 81-MOPS controller

Authors: Eiji Ogura, Masatoshi Takashima, Daisuke Hiranaka, Toshiro Ishikawa, Yukio Yanagita, Shuji Suzuki, Tokuya Fukuda, Toshiyuki Ishii

500-Mb/s nonprecharged data bus for high-speed DRAM's

Authors: Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Shigetoshi Wakayama, Hisakatsu Araki, Tsz-Shing Cheung, Kohtaroh Gotoh, Tadao Aikawa, Takaaki Suzuki, Masao Taguchi, Takeshi Imamura

A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell

Authors: Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada

A 1.0-GHz single-issue 64-bit powerPC integer processor

Authors: Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Authors: Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator

Authors: Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing

Authors: Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino

A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μm GaAs MESFET's

Authors: Koichi Murata, Taiichi Otsuji, Mikio Yoneyama, Masami Tokumitsu

Wide-band transimpedance amplifiers using AlGaAs/InxGa1-xAs pseudomorphic 2-DEG FET's

Authors: Yasuyuki Suzuki and Kazuhiko Honjo

A GaAs upconverter MMIC with an automatic gain control amplifier for 1.9 GHz PHS

Authors: Huainan Ma, Sher Jiun Fang, Fujiang Lin, Khen-Sang Tan, Junichi Shibata, Atsushi Tamura, Hiroshi Nakamura

A highly miniaturized front-end HIC for 1.9 GHz bands

Authors: Tadayoshi Nakatsuka, Junji Itoh, Takayuki Yoshida, Mitsuru Nishitsuji, Tomoya Uda, Osamu Ishikawa

An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs

Authors: Taiichi Otsuji, Koichi Murata, Takatomo Enoki, Yohtaro Umeda

50-GHz-bandwidth baseband amplifiers using GaAs-based HBTs

Authors: Yasuyuki Suzuki, Hidenori Shimawaki, Yasushi Amamiya, Nobuo Nagano, Takaki Niwa, Hitoshi Yano, Kazuhiko Honjo

Very-high-speed InP/InGaAs HBT ICs for optical transmission systems

Authors: Hideyuki Suzuki, Koichi Watanabe, Kyosuke Ishikawa, Hiroshi Masuda, Kiyoshi Ouchi, Tomonori Tanoue, Ryoji Takeyari

An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI

Authors: Kiyoto Watabe, Hajime Akiyama, Tomohide Terashima, Masakazu Okada, Shinji Nobuto, Masao Yamawaki, Sotoju Asa

An HBT MMIC power amplifier with an integrated diode linearizer for low-voltage portable phone applications

Authors: Toshihiko Yoshimasu, Masanori Akagi, Noriyuki Tanba, Shinji Hara

Computational sensor for visual tracking with attention

Authors: Vladimir Brajovic and Takao Kanade

A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's

Authors: Hiroki Morimura and Nobutaro Shibata

A 156-Mb/s CMOS optical receiver for burst-mode transmission

Authors: Makoto Nakamura, Noboru Ishihara, Yukio Akazawa

A multipage cell architecture for high-speed programming multilevel NAND flash memories

Authors: Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa

The impact of scaling down to deep submicron on CMOS RF circuits

Authors: Qiuting Huang, Francesco Piazza, Paolo Orsatti, Tatsuya Ohguro

An access-sequence control scheme to enhance random-access performance of embedded DRAM's

Authors: Kazushige Ayukawa, Takao Watanabe, Susumu Narita

400-MHz random column operating SDRAM techniques with self-skew compensation

Authors: Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

Authors: Hiroshi Kawaguchi and Takayasu Sakurai

A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's

Authors: Shoichiro Kawashima, Toshihiko Mori, Ryuhei Sasagawa, Makoto Hamaminato, Shigetoshi Wakayama, Kazuo Sukegawa, Isao Fukushi

A 2-V 1.9-GHz Si down-conversion mixer with an LC phase shifter

Authors: Hiroshi Komurasaki, Hisayasu Sato, Nagisa Sasaki, Takahiro Miki

CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters

Authors: Koji Kotani, Tadashi Shibata, Tadahiro Ohmi

A data-transition look-ahead DFF circuit for statistical reduction in power consumption

Authors: Masafumi Nogawa and Yusuke Ohtomo

High-density chain ferroelectric random access memory (chain FRAM)

Authors: Daisaburo Takashima and Iwao Kunishima

A sophisticated analysis procedure for an MMIC phase shifter

Author: Kohei Fujii

Variable supply-voltage scheme for low-power high-speed CMOS digital design

Authors: Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama

A 25 Ms/s 8-b-10 Ms/s 10-b CMOS data acquisition IC for digital storage oscilloscopes

Authors: Naoya Kusayanagi, Toru Choi, Masaya Hiwatashi, Masahiro Segami, Yasukazu Akasaka, Tadashi Wakabayashi

A mixed-signal array processor with early vision applications

Authors: David A. Martin, Hae-Seung Lee, Ichiro Masaki

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Authors: Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa, Masahiro Kanazawa, Makoto Ichida, Kazutaka Nogami

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

Authors: Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's

Authors: Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi

Resonant-tunneling diode and HEMT logic circuits with multiple thresholds and multilevel output

Authors: Takao Waho, Kevin J. Chen, Masafumi Yamamoto

A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication

Authors: Akihiro Yamagishi, Masayuki Ishikawa, Tsuneo Tsukahara, Shigeru Date

20-Mb/s erase/record flash memory by asymmetrical operation

Authors: Takayuki Kawahara, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, Katsutaka Kimura

Internal voltage generator for low voltage, quarter-micrometer flash memories

Authors: Takayuki Kawahara, Syun-ichi Saeki, Yusuke Jyouno, Naoki Miyamoto, Takashi Kobayashi, Katsutaka Kimura

A PWM signal processing core circuit based on a switched current integration technique

Authors: Makoto Nagata, Jun Funakoshi, Atsushi Iwata

Authors' Reply

Authors: Tadao Nakagawa and Hideyuki Nosaka

A 256-Mb SDRAM using a register-controlled digital DLL

Authors: Atsushi Hatakeyama, Hirohiko Mochizuki, Tadao Aikawa, Masato Takita, Yuki Ishii, Hironobu Tsuboi, Shin-ya Fujioka, Shusaku Yamaguchi, Makoto Koga, Yuji Serizawa, Koichi Nishimura, Kuninori Kawabata, Yoshinori Okajima, Michiari Kawano, Hideyuki Kojima, Kazuhiro Mizutani, Toru Anezaki, Masatomo Hasegawa, Masao Taguchi

A 1/4-inch 330 K square pixel progressive scan CMOS active pixel image sensor

Authors: Yoshinori Iida, Eiji Oba, Keiji Mabuchi, Nobuo Nakamura, Hiroki Miura

A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras

Authors: Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Keijiro Umehara, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa

A 1-V programmable DSP for wireless communications [CMOS]

Authors: Wai Lee, Paul E. Landman, Brock Barton, Shigeshi Abiko, Hiroshi Takahashi, Hiroyuki Mizuno, Shigetoshi Muramatsu, Kenichi Tashiro, Masahiro Fusumada, Luat Pham, Frederic Boutaud, Emmanuel Ego, Girolamo Gallo, Hiep Tran, Carl Lemonds, Albert Shih, Mahalingam Nandakumar, Robert H. Eklund, Ih-Chin Chen

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

Authors: Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina

A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O

Authors: Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto

A four-level storage 4-Gb DRAM

Authors: Takashi Okuda and Tatsunori Murotani

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

Authors: Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma

On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM

Authors: Satoru Tanoi, Yasuhiro Tokunaga, Tetsuya Tanabe, Kazuhiko Takahashi, Atsuhiko Okada, Masahiro Itoh, Yoshiki Nagatomo, Yoshio Ohtsuki, Masaru Uesugi

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

Authors: Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto

A 2.7-V GSM RF transceiver IC

Authors: Taizo Yamawaki, Masaru Kokubo, Kiyoshi Irie, Hiroaki Matsui, Kazuaki Hori, Takefumi Endou, Hiroshi Hagisawa, Tomio Furuya, Yoshimi Shimizu, Makoto Katagishi, Julian Robert Hildersley

A 0.5-V MTCMOS/SIMOX logic gate

Authors: Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya

An ultralow power CMOS/SIMOX programmable counter LSI

Authors: Yuichi Kado, Hideo Ohno, Mitsuru Harada, K. Deguchi, Toshiaki Tsuchiya

Flexible test mode approach for 256-Mb DRAM

Authors: Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik

Error suppressing encode logic of FCDL in a 6-b flash A/D converter

Authors: Koichi Ono, Tatsuji Matsuura, Eiki Imaizumi, Hisashi Okazawa, Ryuushi Shimokawa

A 50-W low distortion GaAs MESFET for digital cellular base stations

Authors: Fuminobu Ono, Zenzo Singu, Kazunori Asano, Junko Morikawa, Masaaki Kuzuhara, Fumiaki Emori

A 1.9-GHz Si-bipolar variable attenuator for PHS transmitter

Authors: Shoji Otaka, Hiroshi Tanimoto, Shuji Watanabe, Tadahiko Maeda

40-Gb/s ICs for future lightwave communications systems

Authors: Taiichi Otsuji, Yuhki Imai, Eiichi Sano, Shunji Kimura, Satoshi Yamaguchi, Mikio Yoneyama, Takatomo Enoki, Yohtaro Umeda

A super-dynamic flip-flop circuit for broad-band applications up to 24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs

Authors: Taiichi Otsuji, Mikio Yoneyama, Koichi Murata, Eiichi Sano

Highly integrated three-dimensional MMIC technology applied to novel masterslice GaAs- and Si-MMICs

Authors: Tsuneo Tokumitsu, Makoto Hirano, Kimiyoshi Yamasaki, Chikara Yamaguchi, Kenjiro Nishikawa, Masayoshi Aikawa

Circuit techniques for 1.5-V power supply flash memory

Authors: Nobuaki Otsuka and Mark A. Horowitz

A dynamic analysis of the Dickson charge pump circuit

Authors: Toru Tanzawa and Tomoharu Tanaka

A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode

Authors: Kazuya Yamanaka, Sumitaka Takeuchi, Shuji Murakami, Masayuki Koyama, Jun Ido, Takashi Fujiwara, Susumu Hirano, Keisuke Okada, Tadashi Sumi

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits

Authors: Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada

A stable programming pulse generator for single power supply flash memories

Authors: Toru Tanzawa and Tomoharu Tanaka

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory

Authors: Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya

2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell

Authors: Hiroshige Hirano, Toshiyuki Honda, Nobuyuki Moriwaki, Tetsuji Nakakuma, Atsuo Inoue, George Nakane, Shigeo Chaya, Tatsumi Sumi

Limitations and challenges of multigigabit DRAM chip design

Authors: Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed

Authors: Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto

A direct digital synthesizer with interpolation circuits

Authors: Tadao Nakagawa and Hideyuki Nosaka

A compact on-chip ECC for low cost flash memories

Authors: Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip

Authors: Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome

A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wireless communications networks

Authors: Mohammad Madihian, Emmanuel Bak, Hiroshi Yoshida, Hiroshi Hirabayashi, Kyotaka Imai, Yasushi Kinoshita, Tohru Yamazaki, Laurent Desclos

A low-power, low-cost bipolar GPS receiver chip

Authors: Anna M. Murphy, Shinichi Tsutsumi, Peter Gaussen

A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range

Authors: Ichiro Fujimori, Kazuo Koyama, David Trager, Fred Tam, Lorenzo Longo

Floating-point datapaths with online built-in self speed test

Authors: Yasuhiko Hagihara, Shigeto Inui, Fuyuki Okamoto, Masato Nishida, Toshihiko Nakamura, Hachiro Yamada

A 10-b, 100-MS/s CMOS A/D converter

Authors: Kwang Young Kim, Naoya Kusayanagi, Asad A. Abidi

A DSP for DCT-based and wavelet-based video codecs for consumer applications

Authors: Kiyoshi Okamoto, Takuya Jinbo, Toshiyuki Araki, Yasuo Iizuka, Hiromasa Nakajima, Minoru Takahata, Hisashi Inoue, Shun-ichi Kurohmaru, Tomonori Yonezawa, Kunitoshi Aono

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's

Authors: Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada

A bipolar low-voltage quarter-square multiplier with a resistive-input based on the bias offset technique

Author: Katsuji Kimura

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic

Authors: Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]

Authors: Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

Authors Reply

Authors: Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko

A 0.25-μm CMOS 0.9-V 100-MHz DSP core

Authors: Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina

An eight-bit prefetch circuit for high-bandwidth DRAM's

Authors: Toshio Sunaga, Koji Hosokawa, Yutaka Nakamura, Manabu Ichinose, Yasuyuki Igarashi

A novel power-off mode for a battery-backup DRAM

Authors: Daisaburo Takashima and Yukihito Oowaki

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

Authors: Hiroyuki Yamada, Masanori Tsunotani, Fumiyasu Kaneyama, Shouhei Seki

A 3-V, 2%-mW multibit current-mode ΣΔ DAC with 100 dB dynamic range

Authors: Toshihiko Hamasaki, Yoshiaki Shinohara, Hitoshi Terasawa, Kou-Ichirou Ochiai, Masaya Hiraoka, Hideki Kanayama

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology

Authors: Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida

A 1.9-GHz single chip IF transceiver for digital cordless phones

Authors: Hisayasu Sato, Kenichi Kashiwagi, Kazuhito Niwano, Tetsuya Iga, Tatsuhiko Ikeda, Koichiro Mashiko, Tadashi Sumi, Koji Tsuchihashi

An offset-free LPF for π/4-shift QPSK signal generator

Authors: Hiroshi Tanimoto, Tetsuro Itakura, Takashi Ueno, Akira Yasuda, Kazuhiro Oda

A single-chip GaAs RF transceiver for 1.9-GHz digital mobile communication systems

Authors: Kazuya Yamamoto, Kosei Maemura, Nobuyuki Kasai, Yutaka Yoshii, Yukio Miyazaki, Masatoshi Nakayama, Noriko Ogata, Tadashi Takagi, Mutsuyuki Otsubo

Design of a one-transistor-cell multiple-valued CAM

Authors: Takahiro Hanyu, N. Kanagawa, Michitaka Kameyama

Design of a one-transistor-cell multiple-valued CAM

Authors: Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama

Low-power video encoder/decoder chip set for digital VCRs

Authors: Katsuya Hasegawa, Kazutake Ohara, Akihisa Oka, Takehiro Kamada, Yasuhiro Nagaoka, Katsuhisa Yano, Eiji Yamauchi, Takao Kashiro, Tomoo Nakagawa

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories

Authors: Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

Authors: Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihira Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Authors: Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

Authors: Tohru Miwa, Hachiro Yamada, Yoshinori Hirota, Toshiya Satoh, Hideki Hara

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators

Authors: Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application

Authors: Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada

A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell

Authors: Masayoshi Ohkawa, Hiroshi Sugawara, Naoaki Sudo, Masaru Tsukiji, Ken-ichiro Nakagawa, Masato Kawata, Ken-ichi Oyama, Toshio Takeshima, Shuichi Ohya

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

Authors: Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John Mark Drynan, Masahiro Komuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko ichinose, Tomoo imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, Takashi Okuda

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

Authors: Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding

Authors: Kazuhito Suguri, Toshihiro Minami, Hiroaki Matsuda, Ritsu Kusaba, Toshio Kondo, Ryota Kasai, Takumi Watanabe, Hidenuri Sato, Nobutarou Shibata, Yutaka Tashiro, Takaaki Izuoka, Atsushi Shimizu, Hiroshi Kotera

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM

Authors: Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI

Authors: Sanroku Tsukamoto, I. Dedic, Toshiaki Endo, K. y. Kikuta, K. Goto, O. Kobayashi

200-MHz superscalar RISC microprocessor

Authors: Nader Vasseghi, Kenneth Yeager, Egino Saito, Mahdi Seddighnezhad

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

Authors: Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta

A low-power 128×1-bit GaAs FIFO for ATM packet switcher

Authors: Hidetoshi Kawasaki and Stephen I. Long

Direct-coupled distributed baseband amplifier IC's for 40-Gb/s optical communication

Authors: Shunji Kimura, Yuhki Imai, Yutaka Miyamoto

High power DPDT antenna switch MMIC for digital cellular systems

Authors: Kazumasa Kohama, Takahiro Ohgihara, Yoshikazu Murakami

A 2.4 Gb/s receiver and a 1: 16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor

Authors: Fumihiko Sato, Hiroshi Tezuka, Masaaki Soda, Takasuke Hashimoto, Tetsuyuki Suzaki, Tom Tatsumi, Takenori Morikawa, Tsutomu Tashiro

A parallel processing chip with embedded DRAM macros

Authors: Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

Authors: Tadashi Maeda, Keiichi Numata, Masahiro Fujii, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa

A 29-ns 64-Mb DRAM with hierarchical array architecture

Authors: Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato

A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme

Authors: Hiroyuki Yamauchi and Akira Matsuzawa

Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor

Authors: Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta

Over-30-GHz limiting amplifier ICs with small phase deviation for optical communication systems

Authors: Makoto Nakamura, Yuhki Imai, Shoji Yamahata, Yohtaro Umeda

Leading-zero anticipatory logic for high-speed floating point addition

Authors: Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Authors: Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto

A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

Authors: Hiroalti Murakami, Naoka Yano, Yukio Ootaguro, Yukio Sugeno, Maki Ueno, Yukinori Muroya, Tsuneo Aramaki

A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication

Authors: Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi

A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier

Authors: Tetsuro Itakura and Tetsuya Iida

A GaAs MMIC chip-set for mobile communications using on-chip ferroelectric capacitors

Authors: Haruhiko Koizumi, Atsushi Noma, Tsuyoshi Tanaka, Kunihiko Kanazawa, Daisuke Ueda

A 1.2 GFLOPS neural network chip for high-speed neural network servers

Authors: Yoshikazu Kondo, Yuichi Koshiba, Yutaka Arima, Mitsuhiro Murasaki, Tuyoshi Yamada, Hiroyuki Amishiro, Hakuro Mori, Kazuo Kyuma

Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability

Authors: Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

Authors: Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko

A GHz MOS adaptive pipeline technique using MOS current-mode logic

Authors: Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada

A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications

Authors: Akilesh Parameswar, Hiroyuki Hara, Takayasu Sakurai

A full bit prefetch DRAM sensing circuit

Author: Toshio Sunaga

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

Authors: Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko

Top-down pass-transistor logic design

Authors: Kazuo Yano, Yasuhiko Sasaki, Kunihito Rikino, Koichi Seki

Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits

Authors: Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta

A 90-MHz 16-Mb system integrated memory with direct interface to CPU

Authors: Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs

Authors: Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki

A current direction sense technique for multiport SRAM's

Authors: Masanori Izumikawa and Masakazu Yamashina

An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

Authors: Hideyuki Kabuo, Minoru Okamoto, Isao Tanaka, Hiroyuki Yasoshima, Shinichi Marui, Masayuki Yamasaki, Toshio Sugimura, Katsuhiko Ueda, Toshihlro Ishikawa, Hidetoshi Suzuki, Ryuichi Asahi

Fault-tolerant designs for 256 Mb DRAM

Authors: Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

Authors: Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto

Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI

Authors: Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina

A 286 MHz 64-b floating point multiplier with enhanced CG operation

Authors: Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

Driving source-line cell architecture for sub-1-V high-speed low-power applications

Authors: Hiroyuki Mizuno and Takahiro Nagano

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

Authors: Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki

A double-level-Vth select gate array architecture for multilevel NAND flash memories

Authors: Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture

Authors: Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ

Authors: Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii

A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory

Authors: Tadaaki Yamauchi, Yoshikazu Morooka, Hideyuki Ozaki

A time digitizer CMOS gate-array with a 250 ps time resolution

Authors: Yasuo Arai and Masahiro Ikeno

A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

Authors: Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima, Masaoki Ishikawa, Muneo Fukaishi, Hikam Hida, Yasuo Ohno

Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage

Authors: Satoshi Sakurai and Mohammed Ismail

A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator

Authors: Tsuneo Tsukahara, Masayuki Ishikawa, Masahiro Muraguchi

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond

Authors: Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

Authors: Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki

A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment

Authors: Shoji Otaka, Takafumi Yamaji, Ryuichi Fujimoto, Chikau Takahashi, Hiroshi Tanimoto

A fully compensated active pull-down ECL circuit with self-adjusting driving capability

Authors: Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko

An adjustment-free single-chip video signal processing LSI for VHS VCR's

Authors: Norihisa Yamamoto, Osamu Nakagawa, Kenji Takebuchi, Yukinori Kitamura

A 10 Mb frame buffer memory with Z-compare and A-blend units

Authors: Kazunari Inoue, Hisashi Nakamura, Hiroyuki Kawai

3.5-Gb/s⨉4-ch Si bipolar LSI's for optical interconnections

Authors: Noboru Ishihara, Shuichi Fujita, Minoru Togashi, Shigeki Hino, Yoshimitsu Arai, Nobuyuki Tanaka, Yoshiji Kobayashi, Yukio Akazawa

A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search

Authors: Kazuya Ishihara, Shinichi Masuda, Shin-ichi Hattori, Hirofumi Nishikawa, Yoshihide Ajioka, Tsuyoshi Yamada, Hiroyuki Amishiro, Shin-ichi Uramoto, Masahiko Yoshimoto, Tadashi Sumi

A 22-kHz multibit switched-capacitor sigma-delta D/A converter with 92 dB dynamic range

Authors: Peicheng Ju, Ken Suyama, Paul F. Ferguson Jr., Wai Lee

High reliability electron-ejection method for high density flash memories

Authors: Takayuki Kawahara, Naoki Miyamoto, Syun-ichi Saeki, Yusuke Jyouno, Masataka Kato, Katsutaka Kimura

Low-noise, high-speed data transmission using a ringing-canceling output buffer

Authors: Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki

A 2.7-4.5 V single chip GSM transceiver RF integrated circuit

Authors: Trudy D. Stetzler, Irving G. Post, Joseph H. Havens, Mikio Koyama

A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits

Authors: Toshiro Takahashi, Makio Uchida, Takahiko Takahashi, Ryozo Yoshino, Masakazu Yamamoto, Nobuh Kitamura

A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D converter

Authors: Michio Yotsuyanagi, Hiroshi Hasegawa, Motoi Yamaguchi, Masaki Ishida, Kazuya Sone

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic

Authors: Takahiro Hanyu and Michitaka Kameyama

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL

Authors: Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

Authors: Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto

An experimental 295 MHz CMOS 4K⨉256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers

Authors: Natsuki Kushiyama, Charles Tan, Richard Clark, Jane Lin, Fred Perner, Lisa Martin, Mark Leonard, Gene Coussens, Kit Cham

A 64-b microprocessor with multimedia support

Authors: Lavi Lev, Andy Charnas, Marc Tremblay, Alexander Dalal, Bruce A. Frederick, Chakra R. Srivatsa, David Greenhill, Dennis L. Wendell, Duy Dinh Pham, Eric Anderson, Hemraj K. Hingarh, Inayat Razzack, James M. Kaku, Ken Shin, Marc E. Levitt, Michael Allen, Philip A. Ferolito, Richard L. Bartolotti, Robert K. Yu, Ronald J. Melanson, Shailesh I. Shah, Sophie Nguyen, Sundari S. Mitra, Vinita Reddy, Vidyasagar Ganesan, Willem J. de Lange

A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM

Authors: Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors

Authors: Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Authors: Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda

A 1-Gb DRAM for file applications

Authors: Tadahiko Sugibayashi, Isao Naritake, Satoshi Utsugi, Kentaro Shibahara, Ryuichi Oikawa, Hidemitsu Mori, Shouichi Iwao, Tatsunori Murotani, Kuniaki Koyama, Shinichi Fukuzawa, Toshiro Itani, Kunihiko Kasama, Takashi Okuda, Shuichi Ohya, Masaki Ogawa

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

Authors: Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto

A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current

Authors: Hiroyuki Yamauchi, Tom Iwata, Akito Uno, Masanori Fukumoto, Tsutomu Fujita

DC to 40-GHz broad-band amplifiers using AlGaAs/GaAs HBT's

Authors: Yasuhiko Kuriyama, Junko Akagi, Tohru Sugiyama, Sadato Hongo, Kunio Tsuda, Norio Iizuka, Masao Obara

A 40-GHz D-type flip-flop using AlGaAs/GaAs HBT's

Authors: Y. Kuriyama, T. Sugiyama, S. Hongo, J. Akagi, K. Tsuda, N. Iizuka, M. Obara

A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-μm GaAs MESFET

Authors: Koichi Murata, Taiichi Otsuji, Eiichi Sano, Masanobu Ohhata, Minoru Togashi, Masao Suzuki

GaAs converter IC's for C-band DBS receivers

Authors: Sadayoshi Yoshida, Kazunari Satoh, Tatsuya Miya, Takeshi Umemoto, Hiromitsu Hirayama, Katsunori Miyagaki, Joseph Leong

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

Authors: Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada

A neuron-MOS neural network using self-learning-compatible synapse circuits

Authors: Tadashi Shibata, Hideo Kosaka, Hiroshi Ishii, Tadahiro Ohmi

Principle and applications of an autocharge-compensated sample and hold circuit

Authors: Takeshi Shima, Tetsuro Itakura, Shigeru Yamada, Hironori Minamizaki, Takeshi Ishioka

A 2/3-in 2 million pixel STACK-CCD HDTV imager

Authors: Hirofumi Yamashita, Michio Sasaki, Shinji Ohsawa, Ryohei Miyagawa, Eiji Ohba, Keiji Mabuchi, Nobuo Nakamura, Nagataka Tanaka, Nahoko Endoh, Ikuko Inoue, Yoshiyuki Matsunaga, Yoshitaka Egawa, Yukio Endo, Tetsuya Yamaguchi, Yoshinori Iida, Akihiko Furukawa, Sohei Manabe, Yoshiki Ishizuka, Hideo Ichinose, Takako Niiyama, Hisanori Ihara, Hidetoshi Nozaki, Isamu Yanase, Naoshi Sakuma, Takeo Sakakubo, Hiroki Honda, Fujio Masuoka, Okio Yoshida, Hiroyuki Tango, Shun-ichi Sano

A 3.0 V 40 Mb/s hard disk drive read channel IC

Authors: Geert A. De Veirman, Shunsaku Ueda, Jackie Cheng, Stephen Tam, Kiyoshi Fukahori, Masafumi Kurisu, Eiji Shinozaki

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications

Authors: Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina

A BiCMOS wired-OR logic

Authors: Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko

Resistive interpolation biasing: a technique for compensating linear variation in an array of MOS current sources

Authors: Srinagesh Satyanarayana and Ken Suyama

Asynchronous transfer mode switching LSI chips with 10-Gb/s serial I/O ports

Authors: Shigeki Hino, Minoru Togashi, Kimiyoshi Yamasaki

Data-dependent logic swing internal bus architecture for ultralow-power LSI's

Authors: Mitsuru Hiraki, Hirotsugu Kojima, Hitoshi Misawa, Takashi Akazawa, Yuji Hatano

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

Authors: Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida

ATM in B-ISDN communication systems and VLSI realization

Authors: Takeo Koinuma and Noriharu Miyaho

Half-swing clocking scheme for 75% power saving in clocking circuitry

Authors: Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki

Cache-processor coupling: a fast and wide on-chip data cache design

Authors: Masato Motomura, Toshiaki Inoue, Hachiro Yamada, Akihiko Konagaya

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

Authors: Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's

Authors: Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki

Present and future directions for multichip module technologies

Author: Toshio Sudo

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits

Authors: Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome

An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's

Authors: Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita

An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC

Authors: Katsufumi Nakamura, Masso Hotta, L. Richard Carley, David J. Allstot

A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates

Authors: Koji Nii, Hideshi Maeno, Tokuya Osawa, Shuhei Iwade, Shinpei Kayano, Hiroshi Shibata

A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer

Authors: Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome

Measurement of digital noise in mixed-signal integrated circuits

Authors: Keiko Makie-Fukuda, Takafumi Kikuchi, Tatsuji Matsuura, Masao Hotta

A variable precharge voltage sensing

Authors: Toshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira

Delay components of a current mode logic circuit and their current dependency

Author: Yutaka Harada

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops

Authors: Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi

Constant-current circuit-biasing technology for GaAs FET IC

Authors: Nobuo Kotera, Kiichi Yamashita, Keiichi Kitamura, Yasushi Hatta

A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique

Authors: Noboru Ishihara and Yukio Akazawa

A 10 bit 20 MS/s 3 V supply CMOS A/D converter

Authors: Masao Ito, Takahiro Miki, Shiro Hosotani, Toshio Kumamoto, Yukihiro Yamashita, Masaki Kijima, Takashi Okuda, Keisuke Okada

A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Authors: Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai

1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping

Authors: Yasuyuki Matsuya and Junzo Yamada

A 20 GHz 8 bit multiplexer IC implemented with 0.5 μm WNx/W-gate GaAs MESFET's

Authors: Toshiki Seshita, Yoshiko Ikeda, Hirotsugu Wakimoto, Kenji Ishida, Toshiyuki Terada, Tokuhiko Matsunaga, Takashi Suzuki, Yoshiaki Kitaura, Naotaka Uchitomi

A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module

Authors: Tsugumichi Shibata, Shunji Kimura, Hideaki Kimura, Yuhki Imai, Yohtaro Umeda, Yukio Akazawa

Si-analog IC's for 20 Gb/s optical receiver

Authors: Masaaki Soda, Hiroshi Tezuka, Fumihiko Sato, Takasuke Hashimoto, Satoshi Nakamura, Tom Tatsumi, Tetsuyuki Suzaki, Tsutomu Tashiro

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor

Authors: Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada

A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC

Authors: Masaki Toyokura, Hisahi Kodama, Eiji Miyagoshi, Koyoshi Okamoto, Masahiro Gion, Takayuki Minemaru, Akihiko Ohtani, Toshiyuki Araki, Hiroshi Takeno, Toshihide Akiyama, Brent Wilson, Kunitoshi Aono

An experimental 256-Mb DRAM with boosted sense-ground scheme

Authors: Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures

Authors: Hisakazu Kotani, Hironori Akamatsu, Yasushi Naito, Toyokazu Fujii, Tohru Iwata, Toshiaki Tsuji, Yutaka Itoh, Norisato Shimizu, Junji Hirase, Yoshiyuki Shibata, Kazuhiro Yamashita, Takashi Hori, Tsutomu Fujita

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator

Authors: Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Authors: Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara

A 30-ns cycle time 4-Mb mask ROM

Author: Toshio Sunaga

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

Authors: Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory

Authors: Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara

A 32-bank 256-Mb DRAM with cache and TAG

Authors: Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM

Authors: Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina

A 3.5 V, 1.3 W GaAs power multi-chip IC for cellular phones

Authors: Masahiro Maeda, Masaaki Nishijima, Hiroyasu Takehara, Chinatsu Adachi, Hiromasa Fujimoto, Osamu Ishikawa

A voltage compensated series-gate bipolar circuit operating at sub-2 V

Authors: Hisayasu Sato, Kimio Ueda, Nagisa Sasaki, Tatsuhiko Ikeda, Koichiro Mashiko

High-performance GaAs switch IC's fabricated using MESFET's with two kinds of pinch-off voltages and a symmetrical pattern configuration

Authors: Hisanori Uda, Takashi Yamada, Tetsuro Sawai, Kaon Nogawa, Yasoo Harada

Frequency mixer with a frequency doubler for integrated circuits

Authors: Katsuji Kimura and Hiroshi Asazawa

An all-analog expandable neural network LSI with on-chip backpropagation learning

Authors: Takashi Morie and Yoshihito Amemiya

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's

Authors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

Authors: Norio Higashisaka, M. Shimada, Akira Ohta, Kenji Hosogi, Y. Tobita, Y. Mitsui

Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit

Authors: Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi

Subthreshold-current reduction circuits for multi-gigabit DRAM's

Authors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

A charge recycle refresh for Gb-scale DRAM's in file applications

Authors: Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

Authors: Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi

Analysis and optimization of BiCMOS gate circuits

Authors: Tadahiro Kuroda, Yoshinori Sakata, Kenji Matsuo

BiCMOS circuit technology for a 704 MHz ATM switch LSI

Authors: Yusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

Authors: Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Kiyomi Naruke, Seiji Yamada, Yoichi Ohshima, Masamitsu Oshikiri, Yohei Hiura, Tomoko Yamane, Kuniyoshi Yoshikawa

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

Authors: Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki

A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates

Authors: Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

Authors: Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment

Author: Akira Matsuzawa

A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter

Authors: Takahiro Miki, Hiroyuki Kouno, Toshio Kumamoto, Yasushi Kinoshita, Takayuki Igarashi, Keisuke Okada

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs

Authors: Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

Authors: Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe

Open/folded bit-line arrangement for ultra-high-density DRAM's

Authors: Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi

Standby/active mode logic for sub-1-V operating ULSI memory

Authors: Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango

A 120-MHz BiCMOS superscalar RISC processor

Authors: Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs

Authors: Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa

An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

Authors: Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki

A 110-MHz/1-Mb synchronous TagRAM

Authors: Yasuo Unekawa, Tsuguo Kobayashi, Tsukasa Shirotori, Yukihiro Fujimoto, Takayoshi Shimazawa, Kazutaka Nogami, Takehiko Nakao, Kazukiro Sawada, Masataka Matsui, Takayasu Sakurai, Man Kit Tang, William A. Huffman

An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM

Authors: Kiyohiro Furutani, Hiroshi Miyamoto, Yoshikazu Morooka, M. Suwa, Hideyuki Ozaki

An outline font rendering processor with an embedded RISC CPU for high-speed hint processing

Authors: Tetsuro Kawata, Kenichi Kawauchi, Nobuaki Miyakawa, Ichiro Kawazome, Hiromi Yasumatsu, Susumu Haga, Masaya Takenaka

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

Authors: Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI

Authors: Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada

A single poly EEPROM cell structure for use in standard CMOS processes

Authors: Katsuhiko Ohsaki, Noriaki Asamoto, Shunichi Takagaki

Design techniques for low-voltage high-speed digital bipolar circuits

Authors: Behzad Razavi, Yusuke Ota, Robert G. Swartz

MOSFET modeling for analog circuit CAD: problems and prospects

Authors: Yannis P. Tsividis and Ken Suyama

A bipolar four-quadrant analog quarter-square multiplier consisting of unbalanced emitter-coupled pairs and expansions of its input ranges

Author: Katsuji Kimura

A high-density data-path generator with stretchable cells

Authors: Yoshiki Tsujihashi, Hisashi Matsumoto, Hidekatsu Nishimaki, Atsushi Miyanishi, Hiroomi Nakao, Osamu Kitada, Shuhei Iwade, Shinpei Kayano, Masayoshi Sakao

Offset compensating bit-line sensing scheme for high density DRAM's

Authors: Yohji Watanabe, Nobuo Nakamura, Shigeyoshi Watanabe

A 0.1- mu A standby current, ground-bounce-immune 1-Mbit CMOS SRAM

Authors: Manabu Ando, Takeshi Okazawa, Hiroshi Furuta, Masayoshi Ohkawa, Junji Monden, Noriaki Kodama, Kazuhiko Abe, Hiroyasu Ishihara, Isao Sasaki

18-GHz 1/8 dynamic frequency divider using Si bipolar technologies

Authors: Haruhiko Ichino, Noboru Ishihara, Masao Suzuki, Shinsuke Konaka

An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H

Authors: Masayuki Ishikawa and Tsuneo Tsukahara

Yield and reliability of MNOS EEPROM products

Authors: Yoshiaki Kamigaki, Shin-Ichi Minami, Takaaki Hagiwara, Kazunori Furusawa, Takeshi Furuno, Ken Uchida, Masaaki Terasawa, Koubu Yamazaki

A single-chip 16-bit 25-ns real-time video/image signal processor

Authors: Katsumi Kikuchi, Yasuaki Nukada, Yasuhiro Aoki, Toshiyuki Kanou, Yukio Endo, Takao Nishitani

A video codec LSI for high-definition TV systems with one-transistor DRAM line memories

Authors: Tomoji Takada, Takeshi Oto, Kazukuni Kitagaki, Naoyuki Hatanaka, Tatsuhiko Demura, Hiromichi Fuji, Toshinori Odaka, Hiroshi Sue, Tadahiro Oku

An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface

Authors: Yutaka Takahashi, Masahiro Takahara, Takayoshi Makabe, Daijiro Inami, Masahiko Ohno, Fujio Nakagawa, Tetsu Koyama, Akihiko Sugiyama, Masao Chatani, Renya Ikeda

A front-end processor for modems

Authors: Kazushige Yamamoto, Osamu Yanaga, Yasuyuki Okuaki

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

Authors: Masakazu Yamashina, Junichi Goto, Fuyuki Okamoto, Koichi Ando, Hachiro Yamada, Tadahiko Horiuchi, Kimiko Nakamura, Tadayoshi Enomoto

A 1.5-V DRAM for battery-based applications

Authors: Masakazu Aoki, Jun Etoh, Kiyoo Itoh, Shin Kimura, Yoshifumi Kawamoto

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register

Authors: Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano

A 60-ns 16-Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance

Authors: Shizuo Chou, Tsuneo Takano, Akio Kita, Fumio Ichikawa, Masaru Uesugi

A 45-ns 16-Mbit DRAM with triple-well structure

Authors: Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Sejii Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto, Koichi Toita

A 4-bit Josephson data processor chip

Authors: Yuji Hatano, Shinichiro Yano, Hiroyuki Mori, Hiroji Yamada, Mikio Hirano, Ushio Kawabe

30-ps 7.5-GHz GaAs MESFET macrocell array

Authors: Masayuki Ino, Minoru Togashi, Shoji Horiguchi, Masahiro Hirayama, Hideki Kataoka

Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic

Authors: Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit

Authors: Katsuyuki Kaneko, Tadashi Okamoto, Masaitsu Nakajima, Yasuhiro Nakakura, Satoshi Gokita, Junji Nishikawa, Yuji Tanikawa, Hiroshi Kadota

Substrate current reduction techniques for BiCMOS DRAM

Authors: Takayuki Kawahara, Goro Kitsukawa, Hisayuki Higuchi, Yoshiki Kawajiri, Takao Watanabe, Kiyoo Itoh, Ryoichi Hori, Yutaka Kobayashi, Tetsuro Matsumoto

A 54000-gate ECL array with substrate power supply

Authors: Masayuki Kokado, Makoto Yoshida, Norihito Miyoshi, Kouichi Suzuki, Matsuo Takaoka, Norihisa Tsuzuki, Hideki Harada

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme

Authors: Shinji Komori, Hidehiro Takata, Todhixuki Tamura, Fumixsdu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Hiroaki Nishikawa, Hiroaki Terada

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Authors: Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

Authors: Masataka Matsui, Hiroshi Momose, Yukihiro Urakawa, Takeo Maeda, Azuma Suzuki, Nobuaki Urakawa, Katsuhiko Sato, Jun'ichi Matsunaga, Kiyofumi Ochii

A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads

Authors: Fumio Miyaji, Yasushi Matsuyama, Yoshik Kanaishi, Katsunori Seno, Takashi Emori, Yoshiaki Hagiwara

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell

Authors: Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka

570-ps 13-mW Josephson 1-kbit NDRO RAM

Authors: Shuichi Nagasawa, Yoshifusa Wada, Mutsuo Hidaka, Hisanao Tsuge, Iichiro Ishida, Shuichi Tahara

A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions

Authors: Takashi Nakayama, Hisao Harigai, Shingo Kojima, Hiroaki Kaneko, Hatsuhide Igarashi, Tsuneo Toba, Yutaka Yamagami, Yoichi Yano

A feedback-type BiCMOS logic gate

Authors: Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Atsuo Watnabe, Shoji Shukuri, Katsuhiro Shimohigashi

A 400 K-transistor CMOS sea-of-gates array with continuous track allocation

Authors: Masatomi Okabe, Yoshihiro Okuno, Takahiko Arakawa, Ichiro Tomioka, Takio Ohno, Tomoyoshi Noda, Masahiro Hatanaka, Yoichi Kuramitsu

Design for reducing alpha-particle-induced soft errors in ECL logic circuitry

Authors: Masatomi Okabe, Makoto Tatsuki, Yutaka Arima, Tadashi Hirao, Yoichi Kuramitsu

A 10-ps resolution, process-insensitive timing generator IC

Authors: Taiichi Otsuji and Naoaki Narumi

A 9-ns 1-Mbit CMOS SRAM

Authors: Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo

A 209 K-transistor ECL gate array with RAM

Authors: Hisayasu Sato, Takashi Nishimura, Makoto Tatsuki, Atsushi Ohba, Shiro Hine, Yoichi Kuramitsu

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM

Authors: Makoto Suzuki, Suguru Tachibana, Atsuo Watanabe, Shoji Shukuri, Hisayuki Higuchi, Takahiro Nagano, Katsuhiro Shimohigashi

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs

Authors: Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

Authors: Kunihiko Yamaguchi, Hiroaki Nanbu, Kazuo Kanetani, Noriyuki Homma, Tohru Nakamura, Kenichi Ohhata, Akihisa Uchida, Katsumi Ogiue

New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier

Authors: Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh

High-density quaternary logic array chip for knowledge information processing systems

Authors: Takahiro Hanyu and Tatsuo Higuchi

A 5.6 MIPS call-handling processor for switching systems

Authors: Takao Hayashi, Yasuaki Saita, Toshiaki Ohno, Takashi Morita, Takuma Fukuda, Shinji Yoshida, Renya Ikeda

A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

Authors: Masao Ida, Naoki Kato, Tohru Takada

Gigahertz-band high-gain GaAs monolithic amplifiers using parallel feedback technique

Authors: Noboru Ishihara, Hiroyuki Kikuchi, Mamoru Ohara

A 300 MHz monolithic video current driver for high-resolution CRT applications

Authors: Kazuo Kato, Hideo Sato, Yasuji Kamata, Kenkichi Yamashita, Seiichi Ueda

1.5 mu m CMOS gate arrays with analog/digital macros designed using common base arrays

Authors: Shigeru Kawada, Yasunori Hara, Toshio Isono, Teruo Inuzuka

A 1 kbit Josephson random access memory using variable threshold cells

Authors: Itaru Kurosawa, Hiroshi Nakagawa, Shin Kosaka, Masahiro Aoyagi, Susumu Takada

A 17 bit oversampling D-A conversion technology using multistage noise shaping

Authors: Yasuyuki Matsuya, Kuniharu Uchimura, Atsushi Iwata, Takao Kaneko

Improvement of soft-error rate in MOS SRAMs

Authors: Shuji Murakami, Katsuki Ichinose, Kenji Anami, Shimpei Kayano

A Josephson 4 bit RALU for a prototype computer

Authors: Hiroshi Nakagawa, Shin Kosaka, Hiroki Kawamura, Itaru Kurosawa, Masahiro Aoyagi, Youichi Hamazaki, Yoshikuni Okada, Susumu Takada

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Authors: Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

New nibbled-page architecture for high-density DRAMs

Authors: Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi

A 20 kbit associative memory LSI for artificial intelligence machines

Authors: Takeshi Ogura, Junzo Yamada, Shin-Ichiro Yamada, Masa'aki Tan'no

A 32 kbyte integrated cache memory

Authors: Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato

An experimental BiCMOS video 10 bit ADC

Authors: Yasuhiro Sugimoto and Satoshi Mizoguchi

An 8 ns 256 K BiCMOS RAM

Authors: Nobuo Tamba, Shuuichi Miyaoka, Masanori Odaka, Katsumi Ogiue, Kouichirou Yamada, Takahide Ikeda, Mitsuru Hirao, Hisayuki Higuchi, Hideaki Uchida

Design of a 32 bit microprocessor, TX1

Authors: Takeji Tokumaru, Eeji Masuda, Chikahiro Hori, Kimiyoshi Usami, Misao Miyata, Jun Iwamura

A new CR-delay circuit technology for high-density and high-speed DRAMs

Authors: Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

VLSI implementation of a variable-length pipeline scheme for data-driven processors

Authors: Tetsuo Yamasaki, Kenji Shima, Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Hiroaki Terada

A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques

Authors: Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara, Tetsuro Matsumoto, Yutaka Kobayashi

A 1920(H)*1035(V) pixel high-definition CCD image sensor

Authors: Eiji Oda, Kenji Nagano, Takanori Tanaka, Nobuhiko Mutoh, Kozo Orihara

A 40-Mpixel/s bit block transfer graphics processor

Authors: Masahiko Sumi, Shigeru Tanaka, Naoyuki Kai, Yuichi Miyazawa, Masato Nagamatsu, Tsutomu Minagawa, Ichiro Nagashima, Tsuneo Hamai, Junji Mori, Tatsuo Noguchi

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance

Authors: Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara, Tetsuro Matsumoto

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode

Authors: Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

A fast-settling op amp with low supply current

Authors: Robert J. Widlar and Mineo Yamatake

An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application

Authors: Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

A dual 4-bit 2-Gs/s full Nyquist analog-to-digital converter using a 70-ps silicon bipolar technology with borosenic-poly process and coupling-base implant

Authors: Valdis E. Garuts, Yeou-Chong Simon Yu, Einar O. Traa, Tadanori Yamaguchi

A built-in Hamming code ECC circuit for DRAMs

Authors: Kiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko

Twisted bit-line architectures for multi-megabit DRAMs

Authors: Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara

Analysis of coupling noise between adjacent bit lines in megabit DRAMs

Authors: Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode

Authors: Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

Authors: Toshihiko Shimizu, Masao Hotta, Kenji Maio, Seiichi Ueda

Si bipolar 2-GHz 6-bit flash A/D conversion LSI

Authors: Tsutomu Wakimoto, Yukio Akazawa, Shinsuke Konaka

Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs

Author: Takayasu Sakurai

Performance limits of mixed analog/digital circuits with scaled MOSFETs

Authors: Eiichi Sano, Tsuneo Tsukahara, Atsushi Iwata

AC-and DC-powered subnanosecond 1-kbit Josephson cache memory design

Authors: Yoshifusa Wada, Mutsuo Hidaka, Shuichi Nagasawa, Ichiro Ishida

A microprogrammable real-time video signal processor (VSP) for motion compensation

Authors: Masakazu Yamashina, Tadayoshi Enomoto, Takemitsu Kunio, Ichiro Tamitani, Hidenobu Harasaki, Yukio Endo, Takao Nishitani, Masao Satoh, Koichi Kikuchi

Josephson pseudorandom bit-sequence generator

Authors: Norio Fujimaki, Takeshi Imamura, Shinya Hasuo

An adaptive line equalizer LSI for ISDN subscriber loops

Authors: Daijiro Inami, Yoshiaki Kuraishi, Shigeo Fushimi, Yutaka Takahashi, Yasuaki Nukada, Shigeharu Kameyama, Akihiro Shiratori

An adaptive line equalizer VLSI using digital signal processing

Authors: Masayuki Ishikawa, Yukio Tanaka, Tadakatsu Kimura

SECOND: synthesis of elementary circuits on demand

Authors: Stewart G. Smith, Michael Keightley, Peter B. Denyer, Shigenori Nagara

A subscriber digital signal processor LSI for PCM applications

Authors: Kazuo Yamakido, Masaru Kokubo, Takahiko Kozaki, Shigeo Nishita, Tatsuya Nishihara, Norio Miyake, Ken'ichi Ohwada

Application and evaluation of direct-write electron beam for ASICs

Authors: Minoru Fujita, Kenji Shiozawa, Tetsurou Kase, Hajime Hayakawa, Fumio Mizuno, Ryo Haruta, Fumio Murai, Shinji Okazaki

A 20-ns 256 K*4 FIFO memory

Authors: Masashi Hashimoto, Masayoshi Nomura, Kenji Sasaki, Katsuo Komatsuzaki, Hiroyuki Fujiwara, Takashi Honzawa, Keiichiro Abe, Tadashi Tachibana, Norihisa Kitagawa

A versatile data string-search VLSI

Authors: Masaki Hirata, Hachiro Yamada, Hajime Nagai, Kousuke Takahashi

1.3- mu m CMOS/bipolar standard cell library for VLSI computers

Authors: Takashi Hotta, Kouzaburou Kurita, Hideo Maejima, Masahiro Iwamura, Shigeya Tanaka, Tadaaki Bandoh, Tatsumi Yamauchi, Atsuo Hotta

A 40-ps high electron mobility transistor 4.1 K gate array

Authors: Kiyoshi Kajii, Yuu Watanabe, Masahisa Suzuki, Isamu Hanyu, Makoto Kosugi, Kouichiro Odani, Takashi Mimura, Masayuki Abe

A low-power 128-MHz VCO for monolithic PLL ICs

Authors: Kazuo Kato, Takashi Sase, Hideo Sato, Ichiro Ikushima, Shin'ichi Kojima

A subnanosecond Josephson 16-bit ALU

Authors: Seigo Kotani, Norio Fujimaki, Takeshi Imamura, Shinya Hasuo

A macro analysis of soft errors in static RAMs

Authors: Yasunobu Nakase, Kenji Anami, Tohru Shiomi, Atsushi Ohba, Shinpei Kayano

A BiCMOS thermal head intelligent driver with density controllers for full-tone rendition printers

Authors: Makoto Tsumura, Royozo Takeuchi, Isao Shimizu

An optimized 1.0- mu m CMOS technology for next-generation channelless gate arrays

Authors: Yukihiro Ushiku, Teruo Kobayashi, Akito Yoshida, Nobuyuki Itoh, Akira Nishiyama, Rempei Nakata

A knowledge-based test generator for standard cell and iterative array logic circuits

Authors: Prab Varma and Yoshihiro Tohma

A monolithic power op amp

Authors: Robert J. Widlar and Mineo Yamatake

A wafer-scale 170000-gate FFT processor with built-in test circuits

Authors: Koichi Yamashita, Akinori Kanasugi, Shinpei Hijiya, Gensuke Goto, Nobutake Matsumura, Takehide Shirato

A DSP line equalizer VLSI for TCM digital subscriber-line transmission

Authors: Hideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba

BiCMOS circuit technology for a high-speed SRAM

Authors: Takakuni Douseki and Yasuo Ohmori

A monolithic video frequency filter using NIC-based gyrators

Authors: Hisatoshi Hagiwara, Masazumi Kumazawa, Shigetaka Takagi, Makoto Furihata, Minoru Nagata, Takeshi Yanagisawa

An experimental large-capacity semiconductor file memory using 16-levels/cell storage

Authors: Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi

An 8-bit 2-ns monolithic DAC

Authors: Tsutomu Kamoto, Yukio Akazawa, Mitsuru Shinagawa

A 32*32-bit multiplier using multiple-valued MOS current-mode circuits

Authors: Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada

An elastic pipeline mechanism by self-timed circuits

Authors: Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Katsuhiko Asada, Hiroaki Terada

Perspective on BiCMOS VLSIs

Authors: Masaharu Kubo, Ikuro Masuda, Kenji Miyata, Katsumi Ogiue

An SOI structure for flash A/D converter

Authors: Toshio Kumamoto, Masao Nakaya, Shigeru Kusunoki, Tadashi Nishimura, Nobuharu Yazawa, Yoichi Akasaka, Yasutaka Horiba

A cyclic A/D converter that does not require ratio-matched components

Authors: Hidetoshi Onodera, Tetsuo Tateishi, Keikichi Tamaru

A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode

Authors: Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Katsuhiko Sato, Tsukasa Shirotori, Masakazu Kakuma, Shigeru Morita, Masaaki Kinugawa, Tetsuya Asami, Kazuhito Narita, Jun-Ichi Matsunaga, Akira Higuchi, Mitsuo Isobe, Tetsuya Iizuka

A 46-ns 1-Mbit CMOS SRAM

Authors: Hiroshi Shimada, Shoichiro Kawashima, Hideo Itoh, Noriyuki Suzuki, Takashi Yabu

Voltage limiters for DRAMs with substrate-plate-electrode memory cells

Authors: Toshio Takeshima, Masahide Takada, Toshiyuki Shimizu, Takuya Katoh, Mitsuru Sakamoto

A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM

Authors: Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara

A 400-MHz DA converter with a 4-bit color map for 2000-line display

Authors: Tomoyuki Watanabe, Kenji Maio, Katsuhiro Norisue, Shin'ichi Hayashi, Seiichi Ueda

A microprogrammable real-time image processor

Authors: Haruyasu Yamada, Ken'ichi Hasegawa, Toshiki Mori, Hiroyuki Sakai, Kunitoshi Aono

A 4-Mbit DRAM with 16-bit concurrent ECC

Authors: Toshio Yamada, Hisakazu Kotani, Junko Matsushima, Michihiro Inoue